I am using the SSP on the LPC2148 as a buffered SPI interface to a
custom CPLD design. I love the FIFO for transactions where I only
need to write to the CPLD. But when I need to read from it, I find
that I need to do a full buffer flush with 8 read of SSPDR for before
I execute my read. This seems like such a waste.
Is there an easier way to flush the FIFO? Is there a way to have
access to the data just read, like a 'RAWSSPDR' register?
Without a fast simple way to clear the buffer, it almost defeats the
point of having one if two way communication is needed.
Senior FPGA Firmware Engineer (Herndon, VA) VT iDirect is dedicated to providing next generation solutions for broadband IP networking via satellite networks. As the leading innovators in this space, our diverse and talented team of Internet, satellite and telecommunications professionals continues to break new ground and create significant opportunities for network operators, for service providers and resellers, and for corporate networking professionals. A Senior FPGA Firmware Engineer at VT iDirect works within the engineering department in a multi-disciplinary SCRUM team using agile framework.