Forums

VPBDIV register

Started by dodge1955 February 28, 2006
Can someone help me with this problem?  See the code below.  I have
UART1 set up to print "Hello Test", but I can't get it to work with a
12Mhz clock, which is what is on the Eval boards.  I am using
currently the Embedded Artists board with the 12Mhz clock.  If I set
the U1DLL to 0x61, which is a 15Mhz clock, and leave VPBDIV = 0 (1/4
processor clock) it works fine (as in the code below).  If I set
VPBDIV = 1 (equal to the processor clock), or if I set the U1DLL to a
value for 12Mhz, it stops working.  So, I guess I don't quite
understand how all those registers work.  Can someone explain?  Is
there something in the Startup code that overrides?  Thanks.

char txbuffer[25];

void my_putchar(char c)
{
   while((U1LSR & 0x20) == 0);    // if not empty, wait
   U1THR = c;
}

void myprint()				  
{
    unsigned char i;

	i = 0;
	while (i < strlen(txbuffer))
	{
       if (((U1LSR & 0x20) != 0) && txbuffer[i])
       {
          U1THR = txbuffer[i++];
       }
	}
}
	void set_up_uart1()
{
   // VPBDIV = 1;     // VPB clk (PCLK) same as processor clock (CCLK)
   PLL0CON = 0;    // not using PLL, since PCLK = oscillator clock
   PLL1CON = 0;    // not used
     
   PINSEL0 |= 0x00010000;
   PCONP |= 0x00000010;

   U1LCR |= 0x80;	       // enable Divisor Latches
   U1FDR = 0x00000010;         // MULVAL = 1, DIVVAL = 0
   U1DLM = 0;	               // 15000000 / 9600 / 16 = 97 = 0x61
   U1DLL = 0x61;	       // 9600 baud, but at 15Mhz
   U1LCR = 0x03;               // 8 bits, 1 stop, no parity, DLAB = 0

   U1FCR = 1;
}
	void 
main()
{
   set_up_uart1();
   sprintf(txbuffer, "Hello Test\r\n");
   while(1)
   {
      myprint();
   }
}
	

An Engineer's Guide to the LPC2100 Series

dodge1955 wrote:
> Can someone help me with this problem?  See the
code below.  I have
> UART1 set up to print "Hello Test", but I can't get it to work
with a
> 12Mhz clock, which is what is on the Eval boards.  I am using
> currently the Embedded Artists board with the 12Mhz clock.  If I set
> the U1DLL to 0x61, which is a 15Mhz clock, and leave VPBDIV = 0 (1/4
> processor clock) it works fine (as in the code below).  If I set
> VPBDIV = 1 (equal to the processor clock), or if I set the U1DLL to a
> value for 12Mhz, it stops working.  So, I guess I don't quite
> understand how all those registers work.  Can someone explain?  Is
> there something in the Startup code that overrides?  Thanks.
> 

> void set_up_uart1()
> {
>    // VPBDIV = 1;     // VPB clk (PCLK) same as processor clock (CCLK)
>    PLL0CON = 0;    // not using PLL, since PCLK = oscillator clock
>    PLL1CON = 0;    // not used
>     
>    PINSEL0 |= 0x00010000;
>    PCONP |= 0x00000010;
> 
>    U1LCR |= 0x80;             // enable Divisor Latches
>    U1FDR = 0x00000010;         // MULVAL = 1, DIVVAL = 0
>    U1DLM = 0;                     // 15000000 / 9600 / 16 = 97 = 0x61
>    U1DLL = 0x61;             // 9600 baud, but at 15Mhz
>    U1LCR = 0x03;               // 8 bits, 1 stop, no parity, DLAB = 0
> 
>    U1FCR = 1;

I think the feed sequences for the PLLs are missing from your code,
so the writes to PLLxCON have no effect.

The things you describe can be explained by PLL0 staying at 60 MHz
from some previous initialisation, so PCLK would be 1/4th of that
at 15 MHz when VPBDIV=0.

By the way, there seems to be something odd in the baudrate calculation
formula given in the LPC214x user manual. The non-fractional part of the
baudrate is calculated as
PCLK/(16x(16xU1DLM + U1DLL))
Instead I would expect something like
PCLK/(16x(256xU1DLM + U1DLL))
because U1DLM and U1DLL are 8-bit values.

Regards,
Bertrik

> By the way, there seems to be something odd in the baudrate
calculation
> formula given in the LPC214x user manual. The
non-fractional part of the
> baudrate is calculated as
> PCLK/(16x(16xU1DLM + U1DLL))
> Instead I would expect something like
> PCLK/(16x(256xU1DLM + U1DLL))
> because U1DLM and U1DLL are 8-bit values.

I referenced errors regarding this equation when I posted my fractional
divider utility a good while back.  There are also some errors in the %error
listing in example table.

The output of correct equation doesn't produce valid results for baud rates
greater than 38400 with PCLK of 3 MHz.  Silicon?  It's not much of a concern
for the LPC214x since core needs to run at minimum 18MHz, but may be an
issue on the LPC2101/2/3.

For those who are not aware my fractional divider utility enumerates every
DLM/DLL/MULVAL/DIVADDVAL register combination to come up with register list
sorted by lowest %error.
	Joel
	
Context correction:

> It's not much of a concern for the LPC214x since
core needs to run at
> minimum 18MHz, but may be an issue on the LPC2101/2/3.

It's not much of a concern for the LPC214x if you are using the USB
peripheral since core needs to run at minimum 18MHz, but may be an issue on
the LPC2101/2/3.

Joel
	
Bertrik,

Thanks.  The feed sequence solved the problem.

Sutton
	--- In lpc2000@lpc2..., Bertrik Sikken <bertrik@...> wrote:
>
> dodge1955 wrote:
> > Can someone help me with this problem?  See the code below.  I have
> > UART1 set up to print "Hello Test", but I can't get it to
work with a
> > 12Mhz clock, which is what is on the Eval boards.  I am using
> > currently the Embedded Artists board with the 12Mhz clock.  If I set
> > the U1DLL to 0x61, which is a 15Mhz clock, and leave VPBDIV = 0 (1/4
> > processor clock) it works fine (as in the code below).  If I set
> > VPBDIV = 1 (equal to the processor clock), or if I set the U1DLL to a
> > value for 12Mhz, it stops working.  So, I guess I don't quite
> > understand how all those registers work.  Can someone explain?  Is
> > there something in the Startup code that overrides?  Thanks.
> > 
> 
> > void set_up_uart1()
> > {
> >    // VPBDIV = 1;     // VPB clk (PCLK) same as processor clock (CCLK)
> >    PLL0CON = 0;    // not using PLL, since PCLK = oscillator clock
> >    PLL1CON = 0;    // not used
> >     
> >    PINSEL0 |= 0x00010000;
> >    PCONP |= 0x00000010;
> > 
> >    U1LCR |= 0x80;             // enable Divisor Latches
> >    U1FDR = 0x00000010;         // MULVAL = 1, DIVVAL = 0
> >    U1DLM = 0;                     // 15000000 / 9600 / 16 = 97 = 0x61
> >    U1DLL = 0x61;             // 9600 baud, but at 15Mhz
> >    U1LCR = 0x03;               // 8 bits, 1 stop, no parity, DLAB = 0
> > 
> >    U1FCR = 1;
> 
> I think the feed sequences for the PLLs are missing from your code,
> so the writes to PLLxCON have no effect.
> 
> The things you describe can be explained by PLL0 staying at 60 MHz
> from some previous initialisation, so PCLK would be 1/4th of that
> at 15 MHz when VPBDIV=0.
> 
> By the way, there seems to be something odd in the baudrate calculation
> formula given in the LPC214x user manual. The non-fractional part of the
> baudrate is calculated as
> PCLK/(16x(16xU1DLM + U1DLL))
> Instead I would expect something like
> PCLK/(16x(256xU1DLM + U1DLL))
> because U1DLM and U1DLL are 8-bit values.
> 
> Regards,
> Bertrik
>
	
I can find where in the LPC214x user's manual says that the minimum 
clock is 18 MHz. It says 10 MHz. Perhaps you were talking about using 
the USB periferal?

Guille

--- In lpc2000@lpc2..., "Joel Winarske" <joelw@...> wrote:
>
> Context correction:
> 
> > It's not much of a concern for the LPC214x since core needs to 
run at
> > minimum 18MHz, but may be an issue on the
LPC2101/2/3.
> 
> It's not much of a concern for the LPC214x if you are using the USB
> peripheral since core needs to run at minimum 18MHz, but may be an 
issue on
> the LPC2101/2/3.
> 
> Joel
>
	
> I can find where in the LPC214x user's manual says that the minimum
> clock is 18 MHz. It says 10 MHz. Perhaps you were
talking about using
> the USB periferal?

Yes, see my follow-up post.  The 18MHz minimum only applies if USB
peripheral is used.
	Joel
	
It is the USB that needs a minimum of 18 MHz, not the core. 
The core can run at 1 MHz, the PLL needs a minimum of 10 MHz and the
USB perpheral needs a minimum VPB frequency of 18 MHz. 
The VPB (or APB in 2103) frequency is the operating frequency divided
by VPBDIV and it defaults to operation frequency divided by 4. So, if
using the USB you need to modify at least the VPBDIV.

hth, Bob

--- In lpc2000@lpc2..., "Guillermo Prandi"
<yahoo.messenger@...> wrote:
>
> I can find where in the LPC214x user's manual says that the minimum 
> clock is 18 MHz. It says 10 MHz. Perhaps you were talking about using 
> the USB periferal?
> 
> Guille
> 
> --- In lpc2000@lpc2..., "Joel Winarske" <joelw@> wrote:
> >
> > Context correction:
> > 
> > > It's not much of a concern for the LPC214x since core needs to 
> run at
> > > minimum 18MHz, but may be an issue on the LPC2101/2/3.
> > 
> > It's not much of a concern for the LPC214x if you are using the USB
> > peripheral since core needs to run at minimum 18MHz, but may be an 
> issue on
> > the LPC2101/2/3.
> > 
> > Joel
> >
>
	
Hello Joel,
	From my reading of pg. 33 of UM LPC214x (below), I concluded the core
can be driven with minimum frequency FOSC MHz (with M=4 and
VBPDIV=1 (i.e. pclkk) one gets 48 MHz USB frequency). Am I
mistaken? Where is the quoted 18 MHz coming from?
Please advise.

"Important: if a particular application is using the USB peripheral,
the PLL1 must be configured since this is the only available source of
the 48 MHz clock required by the USB. This limits the selection of
FOSC to either 12 MHz, 16 MHz or 24 MHz."

Best regards

Roger
	--- In lpc2000@lpc2..., "Joel Winarske" <joelw@...> wrote:
>
> Context correction:
> 
> > It's not much of a concern for the LPC214x since core needs to run at
> > minimum 18MHz, but may be an issue on the LPC2101/2/3.
> 
> It's not much of a concern for the LPC214x if you are using the USB
> peripheral since core needs to run at minimum 18MHz, but may be an
issue on
> the LPC2101/2/3.
> 
> Joel
>
	
Hi Roger,

> From my reading of pg. 33 of UM LPC214x (below), I
concluded the core
> can be driven with minimum frequency FOSC MHz (with M=4 and
> VBPDIV=1 (i.e. pclkk) one gets 48 MHz USB frequency). Am I
> mistaken? Where is the quoted 18 MHz coming from?
> Please advise.

USB peripheral powered off:
10MHz minimum

USB peripheral powered on:
18MHz minimum

Section 14.6.2 in the User Manual:

"
14.6.2 Register Map
The following registers are located in the AHB clock domain. The minimum AHB
clock frequency should be 18MHz. They can be accessed directly by the CPU.
All registers are 32 bit wide and aligned in the word address boundaries.
USB slave mode registers are located in the address region 0xE0090000 to
0xE009004C. All unused address in this region reads DEADABBA.
"

Operating current takes a nice jump with PLL1 on.
	Joel