> 1/ Is this spurious interrupt problem an error in LPC implementation of
> VIC or is it an error in ARM Primecell VIC specifications itself?
> 2/ Can you tell us if there are any other ARM cores with VIC that also
> suffer from spurious interrupts problem that the LPC suffers from?
The Atmel AIC has the same problem.
And though I just start using it the ST STR7 EIC also.
If an interrupt request needs some cycles to propagate through
peripheral -> (VIC|AIC|EIC) -> Core it is very likely that you
are able to disable the interrupt source before the VIC could
evaluate the source => spurious interrupt.
BTW: It is not an ARM problem. Coldfire CPUs do have the same problem.