Using timer one for pwm.
Durring my research of the timer1 and timer 0 functions, I have come to
the conclusion that if using 3 match registers for generating the pwm
outputs, and then using the third match reg for the cycle length to
reset the pwm. Am I correct in setting up the MCR register to allow the
third match register to clear the timer counter?
Or is their a hardware function not documented that does the
housekeeping automatically and resets the timer counter when any match
register is used as the cycle length counter.
The only reason I bring this up is to the following:
um10161 users manual
The doc says page 196 15.5.12 sec para "the timer is reset by the match
reg that is configured to set the pwm cycle length".
Any help on this issue would be great!