--- In l..., "Gus" wrote:
>
> ok! 3 days of work and got it to work but I just need one question
> answered if anyone can help. philips people..help please!
>
> Why you need to set the clock divider (SSPCPSR)in slave mode?
> When master, you define the clock speed but what about slave?
>

SSPCPSR value affect RTIM in SSPIMSC. If i set CPSDVSR on 12 i get
interrupt about every 7us. If i set it on 254 i get interrupt about
every 141us. And if i set it on 2 i get interrupt about every 2,2 us.
My PCLK is 57,2 MHz. Therefore i think RTIM = CPSDVSR * 32 / PCLK

My chip is LPC2132.

i don't know, if CPSDVSR under 12 are allowed. Start a New Thread

--- In l..., "alexnoname27" wrote:
>
> --- In l..., "Gus" wrote:
> >
> > ok! 3 days of work and got it to work but I just need one question
> > answered if anyone can help. philips people..help please!
> >
> > Why you need to set the clock divider (SSPCPSR)in slave mode?
> > When master, you define the clock speed but what about slave?
> > SSPCPSR value affect RTIM in SSPIMSC. If i set CPSDVSR on 12 i get
> interrupt about every 7us. If i set it on 254 i get interrupt about
> every 141us. And if i set it on 2 i get interrupt about every 2,2 us.
> My PCLK is 57,2 MHz. Therefore i think RTIM = CPSDVSR * 32 / PCLK
>
> My chip is LPC2132.
>
> i don't know, if CPSDVSR under 12 are allowed.
>
Since last couple of days I have been trying to implement the SSP
driver in slave mode, preferably interrupt based.

I have been wondering about the need for setting the SSPCPSR register
in slave mode. May be the above explanation is correct. However this
would matter only if the slave driver is being implemented in
interrupt mode, I guess SSPCPSR setting is irrelevant in poll mode.

-Ashwin Start a New Thread