--- In l..., "roger_lynx" wrote:
> And if you were looking specifically for PLL jitter,
where would you
> look at?
Look at the eye pattern of any signal generated by MCU, for example
PWM. You need to ensure you are not synchronising exactly on PLL
divisor rate or it will appear jitter free. So if you are dividing by
16, sync on every 17th pulse and you get the full eye pattern in just
16 overlays.
> When you say "sustained operation", do you mean over
the entire
> (specified) temp. range?
Not in this case. When DUT was subjected to arbitrary frequency and
duty ratios down to 1MHz, I do not rememner any of the observations
suggested that PLL capture failed. Thus I said it should work okay
with 3.68 MHz crystal.
I did not question the original information I got that said PLL range
is 1-50 MHz and that it is was specified to end user (in user manuals)
as 10-25 MHz.
Now that NXP_apps has clarified that 1-50 MHz applies to oscillator,
not PLL, anyone planning to run with less than 10 MHz crystal should
do burn in tests to be sure.
Jaya
LPC2124's PLL working with 3.68Mhz fosc??
Started by ●October 19, 2006
Reply by ●October 20, 20062006-10-20
Reply by ●October 20, 20062006-10-20
--- In l..., "jayasooriah"
wrote:
>
> --- In l..., "roger_lynx" wrote:
> > And if you were looking specifically for PLL jitter, where would
you
> > look at?
>
> Look at the eye pattern of any signal generated by MCU, for example
> PWM. You need to ensure you are not synchronising exactly on PLL
> divisor rate or it will appear jitter free. So if you are
dividing by
> 16, sync on every 17th pulse and you get the full eye pattern in
just
> 16 overlays.
>
> > When you say "sustained operation", do you mean over the entire
> > (specified) temp. range?
>
> Not in this case. When DUT was subjected to arbitrary frequency
and
> duty ratios down to 1MHz, I do not rememner any of the observations
> suggested that PLL capture failed. Thus I said it should work okay
> with 3.68 MHz crystal.
>
> I did not question the original information I got that said PLL
range
> is 1-50 MHz and that it is was specified to end user (in user
manuals)
> as 10-25 MHz.
>
> Now that NXP_apps has clarified that 1-50 MHz applies to
oscillator,
> not PLL, anyone planning to run with less than 10 MHz crystal
should
> do burn in tests to be sure.
>
> Jaya
>
Regardless of how much testing you do, you clearly need to be aware
that following this recommendation is ignoring specific information
from NXP that problems have been seen with the PLL when the source
clock is outside the specified range of 10-25 Mhz.
Brendan.
wrote:
>
> --- In l..., "roger_lynx" wrote:
> > And if you were looking specifically for PLL jitter, where would
you
> > look at?
>
> Look at the eye pattern of any signal generated by MCU, for example
> PWM. You need to ensure you are not synchronising exactly on PLL
> divisor rate or it will appear jitter free. So if you are
dividing by
> 16, sync on every 17th pulse and you get the full eye pattern in
just
> 16 overlays.
>
> > When you say "sustained operation", do you mean over the entire
> > (specified) temp. range?
>
> Not in this case. When DUT was subjected to arbitrary frequency
and
> duty ratios down to 1MHz, I do not rememner any of the observations
> suggested that PLL capture failed. Thus I said it should work okay
> with 3.68 MHz crystal.
>
> I did not question the original information I got that said PLL
range
> is 1-50 MHz and that it is was specified to end user (in user
manuals)
> as 10-25 MHz.
>
> Now that NXP_apps has clarified that 1-50 MHz applies to
oscillator,
> not PLL, anyone planning to run with less than 10 MHz crystal
should
> do burn in tests to be sure.
>
> Jaya
>
Regardless of how much testing you do, you clearly need to be aware
that following this recommendation is ignoring specific information
from NXP that problems have been seen with the PLL when the source
clock is outside the specified range of 10-25 Mhz.
Brendan.
Reply by ●October 20, 20062006-10-20
--- In l..., "Brendan Murphy"
> Regardless of how much testing you do, you clearly need to be aware
> that following this recommendation is ignoring specific information
> from NXP that problems have been seen with the PLL when the source
> clock is outside the specified range of 10-25 Mhz.
You clearly need to be aware that the objective specification and
recommended specifications to the end user can be very different.
Jaya
> Regardless of how much testing you do, you clearly need to be aware
> that following this recommendation is ignoring specific information
> from NXP that problems have been seen with the PLL when the source
> clock is outside the specified range of 10-25 Mhz.
You clearly need to be aware that the objective specification and
recommended specifications to the end user can be very different.
Jaya
Reply by ●October 24, 20062006-10-24
>
> Ooops,
>
> I happen to know that the PLL is specified from 10-25 MHz input
> only, not from 1-50 MHz! The on-chip ciruit (basically an
> inverter)
> needed to make an external crystal run can support 1-50 MHz, not
> the PLL.
> We did test the PLL below 10 MHz and it locked reliably at least
> down to 5 MHz. There were no thorough tests done below 5 MHz as
> this
> is already way out of spec. What we could see, the jitter
> increased
> a lot when using the PLL with 5 MHz input.
> To get the reset problem fixed on the 2124, you actually need to
> follow the instructions in the Errata Sheet, a double reset with
> the
> given minimum time in between will fix it.
>
> There is also a version LPC2124/00 which has the startup problem
> fixed in hardware.
>
> It is however correct that a lower external input frequency
> reduces
> the likelyhood of the startup problem to occur.
>
> nxp_apps
>
OK, Thanks,
These are some LPC2124 boards returned from customer... :(
I cannot change the circuit.
I will use 7.3Mhz fsoc, and wire a DIP8 WatchDog
Timer if I can find someway to "spider" it... :)
Regards
> Ooops,
>
> I happen to know that the PLL is specified from 10-25 MHz input
> only, not from 1-50 MHz! The on-chip ciruit (basically an
> inverter)
> needed to make an external crystal run can support 1-50 MHz, not
> the PLL.
> We did test the PLL below 10 MHz and it locked reliably at least
> down to 5 MHz. There were no thorough tests done below 5 MHz as
> this
> is already way out of spec. What we could see, the jitter
> increased
> a lot when using the PLL with 5 MHz input.
> To get the reset problem fixed on the 2124, you actually need to
> follow the instructions in the Errata Sheet, a double reset with
> the
> given minimum time in between will fix it.
>
> There is also a version LPC2124/00 which has the startup problem
> fixed in hardware.
>
> It is however correct that a lower external input frequency
> reduces
> the likelyhood of the startup problem to occur.
>
> nxp_apps
>
OK, Thanks,
These are some LPC2124 boards returned from customer... :(
I cannot change the circuit.
I will use 7.3Mhz fsoc, and wire a DIP8 WatchDog
Timer if I can find someway to "spider" it... :)
Regards