SSP as SPI Slave (LPC2148) strange behaviour

Started by xyphro4 January 5, 2007
Hello!

I'm currently trying to use the SSP of an LPC2148 as SPI Slave. I set
it up with theese values:



I receive data using polling with this small function:



The Master connected to the SPI1 lines sends continously 8 byte pakets:

SSEL: ---________________________________---------...
Data: <00><01><02><03><04><05><06><07>

The strange thing is that I always receive just the First value of
this packet, the following Bytes are not received allthough I did set
the correct Bitwidth.

When sending the data like this:

SSEL: ---____---____---____---____---...
Data: <00> <01> <02> <03>

I receive all values.

Unfortunately it is absolutely not possible to modify the Master
behaviour to take SSEL high after every single byte.

Usually the SSEL signal is used for Bit and Packet synchronization and
it is okay to leave it low during complete data packets for all other
SPIs that I have programmed before. Some higher level SPI protocolls
can also not be realized with such a strange behaviour and missing
ability for packet synchronization.

Looking at the Primcell PL022 documentation from Arm did also not give
me a hint.

Is anyone able to help?

Best regards,

Kai

An Engineer's Guide to the LPC2100 Series

Hi
May the foll. lines help you : This is relevent if CPHA=0, CPOL=0 and
not when CPHA = 1 .
in the case of continuous back-to-back transmissions, the SSEL signal
must be pulsed HIGH between each data word transfer. This is because
the slave select pin freezes the data in its serial peripheral
register and does not allow it to be altered if the
CPHA bit is logic zero. Therefore the master device must raise the
SSEL pin of the slave device between each data transfer to enable the
serial peripheral data write.

Suvidh
According to Chapter 13, paragraph 3.4 of the LPC2148 User's Manual
the Motorola SPI format requires Slave Select to go high between each
byte of the data transfer. The National Semiconductor Microwire
format does allow continuous byte transmission without toggling the
select signal. That is documented in paragraph 3.8 of Chapter 13. Is
there any chance that your master is actually using the National
Semiconductor Microwire format? There is a lot of similarity between
the two protocols.

-- Dave
suvidhk wrote:
>
> Hi
> May the foll. lines help you : This is relevent if CPHA=0, CPOL=0 and
> not when CPHA = 1 .
>
> in the case of continuous back-to-back transmissions, the SSEL signal
> must be pulsed HIGH between each data word transfer. This is because
> the slave select pin freezes the data in its serial peripheral
> register and does not allow it to be altered if the
> CPHA bit is logic zero. Therefore the master device must raise the
> SSEL pin of the slave device between each data transfer to enable the
> serial peripheral data write.
>

Hmm, that is something I'd not though of, I will have to be carefull of
that in an upcoming design. From the LPC2138 User Manual:

"When a device is a slave, and CPHA is set to 0, the transfer starts
when the SSEL signal goes active, and ends when SSEL goes inactive. When
a device is a slave, and CPHA is set to 1, the transfer starts on the
first clock edge when the slave is selected, and ends on the last clock
edge where data is sampled."

I'll be using the LPC2214 instead of LPC2138, but it sounds as if all
the LPC2000 family does this.
TomW
--
Tom Walsh - WN3L - Embedded Systems Consultant
http://openhardware.net http://cyberiansoftware.com http://openzipit.org
"Windows? No thanks, I have work to do..."
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