Forums

LPC23xx UARTx CTI interrupt problem

Started by Ilian May 23, 2007
Hi,

I'm using UART2 on my LPC2368 board to receive data from other device.
I note that sometimes uart is blocking. The CTI interrupt is always
assetred LSR register indicate there is no data in FIFO (i.e. RDR bit
= 0) and the interrutp can not be cleared (read from UxRBR). And this
crash my system. I investigate problem and I've found this is general
BUG in LPC and in ARM. There is a problem "solution" at AN10414_1.pdf,
but it's concerned for smallest lpc 21xx and so on. In forum
:http://tech.groups.yahoo.com/group/lpc2000/message/14342
reccomends the same way to solve that problem. But the problem is that
in LPC23xx we haven't VICDefVectAddr register so we cann't use :
"
void default_interrupt_handler(void)
{
return;
}

The VIC needs to be initialised with something like:

VICDefVectAddr = (unsigned int) default_interrupt_handler;
"

I try many ways to avoid this problem but currently without a result.

Does someone knows sure way to avoid this problem ?
Is there any code for Uartx on LPC23xx that handles that situation ?

Thanks in advance.
Ilian

An Engineer's Guide to the LPC2100 Series

Yesterday, after setting the "Hardware, halt after delay(ms)" parameter in
my IAR 4.41A debugger to 50 msec, my board became very unstable generating
continuous RX CTI interrupts. Then I started investigating the cause and
observed exact same behaviour which is CTI flag gets set as the interrupt
cause however, no corresponding RDR in LSR register. I did not now this was
because of a bug in UART, I guessed though.

Luckly it took half an hour to resolve it. My original code was (just giving
the relevant section):

switch(UIIR & 0x0f) { // check source
of interrupt

.

.

.

case UINT_RDA : // received data
ready is by rx trigger level

case UINT_CTI : // rx timeout is
by 4 char + 12 bit delay timer

while((Stat=ULSR) & U_RDR) {

Temp=URBR; // read received
byte off the rxfifo

if(!(Stat & U_RXERR)) // process data
only if no rx error

Prot->RxIsrHandler(Temp); // protocol
handles received data

}

break;

.

.

.

}

And the new one that resolved the problem:

switch(UIIR & 0x0f) { // check source
of interrupt

.

.

.

case UINT_RDA : // received data
ready is by rx trigger level

case UINT_CTI : // rx timeout is
by 4 char + 12 bit delay timer

while(true) {

Stat=ULSR; // get line
status

Temp=URBR; // read received
byte off the rxfifo

if(Stat & U_RDR) { // rxfifo
contains characters

if(!(Stat & U_RXERR)) // process data
only if no rx error

Prot->RxIsrHandler(Temp);

}

else

break;

}

break;

.

.

.

}

The idea is to read RBR no matter what the LSR RBR bit is. This fix resolved
the problem.

The strange thing is the problem does not occur when "Hardware, halt after
delay(ms)" is set to 150 ms or more.

Anyhow, hope the above fix works out for you as well

Kerem

From: l... [mailto:l...] On Behalf Of
Ilian
Sent: Wednesday, May 23, 2007 1:06 PM
To: l...
Subject: [lpc2000] LPC23xx UARTx CTI interrupt problem

Hi,

I'm using UART2 on my LPC2368 board to receive data from other device.
I note that sometimes uart is blocking. The CTI interrupt is always
assetred LSR register indicate there is no data in FIFO (i.e. RDR bit
= 0) and the interrutp can not be cleared (read from UxRBR). And this
crash my system. I investigate problem and I've found this is general
BUG in LPC and in ARM. There is a problem "solution" at AN10414_1.pdf,
but it's concerned for smallest lpc 21xx and so on. In forum
:http://tech.groups.yahoo.com/group/lpc2000/message/14342
reccomends the same way to solve that problem. But the problem is that
in LPC23xx we haven't VICDefVectAddr register so we cann't use :
"
void default_interrupt_handler(void)
{
return;
}

The VIC needs to be initialised with something like:

VICDefVectAddr = (unsigned int) default_interrupt_handler;
"

I try many ways to avoid this problem but currently without a result.

Does someone knows sure way to avoid this problem ?
Is there any code for Uartx on LPC23xx that handles that situation ?

Thanks in advance.
Ilian
It's works fine now !

Thanks a lot Kerem !

Regards,
Ilian

Kerem Or wrote: Yesterday, after setting the "Hardware, halt after delay(ms)" parameter in
my IAR 4.41A debugger to 50 msec, my board became very unstable generating
continuous RX CTI interrupts. Then I started investigating the cause and
observed exact same behaviour which is CTI flag gets set as the interrupt
cause however, no corresponding RDR in LSR register. I did not now this was
because of a bug in UART, I guessed though.

Luckly it took half an hour to resolve it. My original code was (just giving
the relevant section):

switch(UIIR & 0x0f) { // check source
of interrupt

.

.

.

case UINT_RDA : // received data
ready is by rx trigger level

case UINT_CTI : // rx timeout is
by 4 char + 12 bit delay timer

while((Stat=ULSR) & U_RDR) {

Temp=URBR; // read received
byte off the rxfifo

if(!(Stat & U_RXERR)) // process data
only if no rx error

Prot->RxIsrHandler(Temp); // protocol
handles received data

}

break;

.

.

.

}

And the new one that resolved the problem:

switch(UIIR & 0x0f) { // check source
of interrupt

.

.

.

case UINT_RDA : // received data
ready is by rx trigger level

case UINT_CTI : // rx timeout is
by 4 char + 12 bit delay timer

while(true) {

Stat=ULSR; // get line
status

Temp=URBR; // read received
byte off the rxfifo

if(Stat & U_RDR) { // rxfifo
contains characters

if(!(Stat & U_RXERR)) // process data
only if no rx error

Prot->RxIsrHandler(Temp);

}

else

break;

}

break;

.

.

.

}

The idea is to read RBR no matter what the LSR RBR bit is. This fix resolved
the problem.

The strange thing is the problem does not occur when "Hardware, halt after
delay(ms)" is set to 150 ms or more.

Anyhow, hope the above fix works out for you as well

Kerem

From: l... [mailto:l...] On Behalf Of
Ilian
Sent: Wednesday, May 23, 2007 1:06 PM
To: l...
Subject: [lpc2000] LPC23xx UARTx CTI interrupt problem

Hi,

I'm using UART2 on my LPC2368 board to receive data from other device.
I note that sometimes uart is blocking. The CTI interrupt is always
assetred LSR register indicate there is no data in FIFO (i.e. RDR bit
= 0) and the interrutp can not be cleared (read from UxRBR). And this
crash my system. I investigate problem and I've found this is general
BUG in LPC and in ARM. There is a problem "solution" at AN10414_1.pdf,
but it's concerned for smallest lpc 21xx and so on. In forum
:http://tech.groups.yahoo.com/group/lpc2000/message/14342
reccomends the same way to solve that problem. But the problem is that
in LPC23xx we haven't VICDefVectAddr register so we cann't use :
"
void default_interrupt_handler(void)
{
return;
}

The VIC needs to be initialised with something like:

VICDefVectAddr = (unsigned int) default_interrupt_handler;
"

I try many ways to avoid this problem but currently without a result.

Does someone knows sure way to avoid this problem ?
Is there any code for Uartx on LPC23xx that handles that situation ?

Thanks in advance.
Ilian



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