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Difference between SPI and SSP in LPC23xx

Started by varuzhandanielyan May 25, 2007
What is the difference between SPI and SSP? They share the same pins
and seems that SSP can do all the SPI can, while being 4 times faster.
Am I wrong?
Varuzhan

An Engineer's Guide to the LPC2100 Series

varuzhandanielyan wrote:
>
> What is the difference between SPI and SSP? They share the same pins
> and seems that SSP can do all the SPI can, while being 4 times faster.
> Am I wrong?
>

( /me looks at his LPC2214 schematic)

Uh, no, they don't seem to "share the same pins".

TomW
--
Tom Walsh - WN3L - Embedded Systems Consultant
http://openhardware.net http://cyberiansoftware.com http://openzipit.org
"Windows? No thanks, I have work to do..."
----------------
TomW....you kill me... lol
Quoting Tom Walsh :

> varuzhandanielyan wrote:
> >
> > What is the difference between SPI and SSP? They share the same pins
> > and seems that SSP can do all the SPI can, while being 4 times faster.
> > Am I wrong?
> > ( /me looks at his LPC2214 schematic)
>
> Uh, no, they don't seem to "share the same pins".
>
> TomW
> --
> Tom Walsh - WN3L - Embedded Systems Consultant
> http://openhardware.net http://cyberiansoftware.com http://openzipit.org
> "Windows? No thanks, I have work to do..."
> ----------------
>
--- In l..., dave@... wrote:
> TomW....you kill me... lol
> Quoting Tom Walsh :
>
> > varuzhandanielyan wrote:
> > >
> > > What is the difference between SPI and SSP? They share the same pins
> > > and seems that SSP can do all the SPI can, while being 4 times
faster.
> > > Am I wrong?
> > >
> >
> > ( /me looks at his LPC2214 schematic)
> >
> > Uh, no, they don't seem to "share the same pins".
> >
> > TomW
> >
> >
> > --
> > Tom Walsh - WN3L - Embedded Systems Consultant
> > http://openhardware.net http://cyberiansoftware.com
http://openzipit.org
> > "Windows? No thanks, I have work to do..."
> > ----------------
> >
> >
>
The SSP0 and SPI0 definitely! share the same pins! More - I could
program the same hardware connection to an external SPI FRAM EEPROM
to work with both interfaces. Nevertheless I want to now different
opinions.
Varuzhan
> -----Original Message-----
> From: l...
> [mailto:l...]On Behalf
> Of varuzhandanielyan
> Sent: Friday, May 25, 2007 12:34 AM
> To: l...
> Subject: [lpc2000] Difference between SPI and SSP in LPC23xx
> What is the difference between SPI and SSP? They share the same pins
> and seems that SSP can do all the SPI can, while being 4 times faster.
> Am I wrong?
> Varuzhan
>

It looks to me like the SSP and SPI are the same speed as either of
them can run at PCLK/2. But, the SSP has a FIFO, and automatic chip
select control, whereas the SPI has neither of these, so using the
FIFO, the SSP could have a faster throughput at the same clock
rate.

Mike
--- In l..., "Michael Anton" wrote:
>
> > -----Original Message-----
> > From: l...
> > [mailto:l...]On Behalf
> > Of varuzhandanielyan
> > Sent: Friday, May 25, 2007 12:34 AM
> > To: l...
> > Subject: [lpc2000] Difference between SPI and SSP in LPC23xx
> >
> >
> > What is the difference between SPI and SSP? They share the same pins
> > and seems that SSP can do all the SPI can, while being 4 times faster.
> > Am I wrong?
> > Varuzhan
> > It looks to me like the SSP and SPI are the same speed as either of
> them can run at PCLK/2. But, the SSP has a FIFO, and automatic chip
> select control, whereas the SPI has neither of these, so using the
> FIFO, the SSP could have a faster throughput at the same clock
> rate.
>
> Mike
>

Is they really the same speed? From the LPC2364/6/8/78 User manual.
For SPI we have:

6.4 SPI Clock Counter Register (S0SPCCR - 0xE002 000C)
This register controls the frequency of a master's SCK. The register
indicates the number
of PCLK cycles that make up an SPI clock. The value of this register
must always be an
even number. As a result, bit 0 must always be 0. The value of the
register must also
always be greater than or equal to 8. Violations of this can result in
unpredictable
behavior.

This give for 72MHz PCLK only 9MHz max

For SSP:

5.5 SSPn Clock Prescale Register (SSP0CPSR - 0xE006 8010, SSP1CPSR
- 0xE003 0010)
This register controls the factor by which the Prescaler divides the
APB clock PCLK to
yield the prescaler clock that is, in turn, divided by the SCR factor
in SSPnCR0, to
determine the bit clock.
Important: the SSPnCPSR value must be properly initialized or the SSP
controller will not
be able to transmit data correctly. In case of an SSP operating in the
master mode, the
CPSDVSRmin = 2, while in case of the slave mode CPSDVSRmin = 12.

This give in master mode 36Mhz.

Varuzhan
> -----Original Message-----
> From: l...
> [mailto:l...]On Behalf
> Of varuzhandanielyan
> Sent: Saturday, May 26, 2007 2:30 AM
> To: l...
> Subject: [lpc2000] Re: Difference between SPI and SSP in LPC23xx
> --- In l..., "Michael Anton" wrote:
> >
> >
> >
> > > -----Original Message-----
> > > From: l...
> > > [mailto:l...]On Behalf
> > > Of varuzhandanielyan
> > > Sent: Friday, May 25, 2007 12:34 AM
> > > To: l...
> > > Subject: [lpc2000] Difference between SPI and SSP in LPC23xx
> > >
> > >
> > > What is the difference between SPI and SSP? They share
> the same pins
> > > and seems that SSP can do all the SPI can, while being 4
> times faster.
> > > Am I wrong?
> > > Varuzhan
> > >
> >
> > It looks to me like the SSP and SPI are the same speed as either of
> > them can run at PCLK/2. But, the SSP has a FIFO, and automatic chip
> > select control, whereas the SPI has neither of these, so using the
> > FIFO, the SSP could have a faster throughput at the same clock
> > rate.
> >
> > Mike
> > Is they really the same speed? From the LPC2364/6/8/78 User manual.
> For SPI we have:
>
> 6.4 SPI Clock Counter Register (S0SPCCR - 0xE002 000C)
> This register controls the frequency of a master's SCK. The register
> indicates the number
> of PCLK cycles that make up an SPI clock. The value of this register
> must always be an
> even number. As a result, bit 0 must always be 0. The value of the
> register must also
> always be greater than or equal to 8. Violations of this can result in
> unpredictable
> behavior.
>
> This give for 72MHz PCLK only 9MHz max

You are correct, I missed the statement about a min value of 8.

>
> For SSP:
>
> 5.5 SSPn Clock Prescale Register (SSP0CPSR - 0xE006 8010, SSP1CPSR
> - 0xE003 0010)
> This register controls the factor by which the Prescaler divides the
> APB clock PCLK to
> yield the prescaler clock that is, in turn, divided by the SCR factor
> in SSPnCR0, to
> determine the bit clock.
> Important: the SSPnCPSR value must be properly initialized or the SSP
> controller will not
> be able to transmit data correctly. In case of an SSP operating in the
> master mode, the
> CPSDVSRmin = 2, while in case of the slave mode CPSDVSRmin = 12.
>
> This give in master mode 36Mhz.
>
> Varuzhan
>

If you knew all of this, why did you ask the question?

Mike