TX FIFO

Started by hodgejackiehank July 6, 2004
As soon as I write a single character to the THRE, Transmit holding
register empty flag in U1LSR is cleared. Either the FIFO is not
enabled or is set to '1', or this is the normal operation (after all,
the FIFO is not **empty**).

In the latter case how do you know if there is still space in the FIFO
to write data?

BTW, while trying to resove this problem I came accross the following
comment in the control register descriptions:

00: trigger level 0 (default='h1)
01: trigger level 1 (default='h4)
10: trigger level 2 (default='h8)
11: trigger level 3 (default='he)
These two bits determine how many receiver UART1 FIFO characters must
be written
before an interrupt is activated. The four trigger levels are defined
by the user at
compilation allowing the user to tune the trigger levels to the FIFO
depths chosen.
0
What exactly does it mean by defined at compile time? Perhaps if I
knew where these levels were configured I would find the answer to my
Tx FIFO problem ?!




An Engineer's Guide to the LPC2100 Series

hodgejackiehank wrote:

> As soon as I write a single character to the THRE, Transmit holding
> register empty flag in U1LSR is cleared. Either the FIFO is not
> enabled or is set to '1', or this is the normal operation (after all,
> the FIFO is not **empty**).
>
> In the latter case how do you know if there is still space in the FIFO
> to write data?
>
> BTW, while trying to resove this problem I came accross the following
> comment in the control register descriptions:
>
> 00: trigger level 0 (default='h1)
> 01: trigger level 1 (default='h4)
> 10: trigger level 2 (default='h8)
> 11: trigger level 3 (default='he)
> These two bits determine how many receiver UART1 FIFO characters must
> be written
> before an interrupt is activated. The four trigger levels are defined
> by the user at
> compilation allowing the user to tune the trigger levels to the FIFO
> depths chosen.
> 0 >
> What exactly does it mean by defined at compile time? Perhaps if I
> knew where these levels were configured I would find the answer to my
> Tx FIFO problem ?! >
>

I also stumbled across this description. Obviously, this is a copy-and-paste
from the description of the '550-UART IP-Core. So, 'compile time' means the time
of the building of the chip, when all the hardware descriptions (in VHDL,
Verilog or whatever) are translated and mapped onto the target technology and
'user' in this case is/are the chip designer(s).
IIRC, somewhere in the user manual is explicitely said that the FIFO holds 16
byte with possible trigger levels being 1, 4, 8 or 14.

Regards,
Jens





> I also stumbled across this description. Obviously, this is a
copy-and-paste
> from the description of the '550-UART IP-Core.

I thought it might be something like that. So given that the FIFO is
preconfigured, how do I know when the FIFO is full?



At 10:28 AM 7/6/04 +0000, you wrote:

> > I also stumbled across this description. Obviously, this is a
>copy-and-paste
> > from the description of the '550-UART IP-Core.
>
>I thought it might be something like that. So given that the FIFO is
>preconfigured, how do I know when the FIFO is full?

In this respect, it behaves as all '550s. When the THRE interrupt fires
the FIFO is empty and you can put up to 16 bytes into it. Something like

case RECEIVE:
for( i = 0; i <16; i++) {
U0THR = buf[i];
}
break;

Oversimplified but it illustrates the point.

AFAIR this is documented in all of a sentence or maybe two.

BTW, I would be very interested if anyone else has run into the missing
THRE interrupt symptoms I've seen.

Robert

" 'Freedom' has no meaning of itself. There are always restrictions,
be they legal, genetic, or physical. If you don't believe me, try to
chew a radio signal. "

Kelvin Throop, III




>
> In this respect, it behaves as all '550s. When the THRE interrupt
fires
> the FIFO is empty and you can put up to 16 bytes into it. Something
like
>

I would like to be able to "top up" the FIFO when possible so that I
can have more time before the next interupt. Trouble is I am not sure
if I am intepreting the flags correctly, the THRE flag appears to be
set even if just 1 byte has been written, so it is no use for seeing
if the FIFO may be topped up.



At 12:00 PM 7/6/04 +0000, you wrote:

> >
> > In this respect, it behaves as all '550s. When the THRE interrupt
>fires
> > the FIFO is empty and you can put up to 16 bytes into it. Something
>like
> >
>
>I would like to be able to "top up" the FIFO when possible so that I
>can have more time before the next interupt. Trouble is I am not sure
>if I am intepreting the flags correctly, the THRE flag appears to be
>set even if just 1 byte has been written, so it is no use for seeing
>if the FIFO may be topped up.

There is no way to know when the transmit FIFO has been partially emptied
(well you could time how long it was since it was last filled).

The THRE flag does just that it flags when the transmitter holding register
is empty. That means that there was nothing in the FIFO to re-fill it.

I can see that a transmitter FIFO would be a useful additional source to
increase the allowable interrupt response latency but there is nothing in
the uart to give it to you.

Robert

" 'Freedom' has no meaning of itself. There are always restrictions,
be they legal, genetic, or physical. If you don't believe me, try to
chew a radio signal. "

Kelvin Throop, III



At 08:10 AM 7/6/04 -0400, you wrote:
>I can see that a transmitter FIFO would be a useful additional source to
>increase the allowable interrupt response latency but there is nothing in
>the uart to give it to you.

Oops, that should be

I can see that a transmitter FIFO threshold interrupt would be ....

Robert

" 'Freedom' has no meaning of itself. There are always restrictions,
be they legal, genetic, or physical. If you don't believe me, try to
chew a radio signal. "

Kelvin Throop, III


Hello all,

I am puzzled by perhaps similar thing re: missing THRE int., FIFO empty?
Can anyone plese help me to see what I do incorrectly?

Polled UART0 works, INT on THRE doesn't.
Timer0 ISR works, though.

The code (snippets below)never makes it to UART_THRE ISR.
I am re-writing INT driven buffered Tx already implemented on another
MCUs.
BTW, I am a newbie on LPC2106, no flames please.

--roger

---ivt.s----
LDR PC, [PC, #-0xFF0] @ load irq vector from vic
LDR PC, FIQ_Addr

-----main.c---

VICIntSelect = 0x0; /* ALL sources selected as IRQ */
VICIntEnable = 0x50; /* TIMER0 and UART0_THRE interrupts enabled */
/* Address of the ISR */
VICVectAddr0 = (unsigned long)IRQ_Timer0_Handler;
VICVectCntl0 = 0x24; /* IRQ for channel 4: TIMER0 : 10 0100 */
VICVectAddr1 = (unsigned long)IRQ_UART0_Tx_Handler;
VICVectCntl1 = 0x26; /* IRQ for channel 6: UART_THRE: 10 0110 */
.
.
.

PINSEL0 = 0x05; // enable UART0 TxD/RxD
UART0_FCR = 0x07; // enable and reset Tx and Rx FIFO
UART0_LCR = 0x83; // 8N1; enable divisor latches access
UART0_DLL = 0x20; // LSB divider for cclk/115200*16=0x20
UART0_DLM = 0x00; // MSB = 0
UART0_IER = 0x02; // enable THRE interrupt
UART0_LCR = 0x03; // disable divisor latches

void __attribute__((interrupt)) IRQ_UART0_Tx_Handler(void)
{
IOCLR =0x00000080; <----- LED, active low never turns ON
...
etc.
}

--- In , Robert Adsett <subscriptions@a...> wrote:
> At 10:28 AM 7/6/04 +0000, you wrote:
>
> > > I also stumbled across this description. Obviously, this is a
> >copy-and-paste
> > > from the description of the '550-UART IP-Core.
> >
> >I thought it might be something like that. So given that the FIFO is
> >preconfigured, how do I know when the FIFO is full?
>
> In this respect, it behaves as all '550s. When the THRE interrupt
fires
> the FIFO is empty and you can put up to 16 bytes into it. Something
like
>
> case RECEIVE:
> for( i = 0; i <16; i++) {
> U0THR = buf[i];
> }
> break;
>
> Oversimplified but it illustrates the point.
>
> AFAIR this is documented in all of a sentence or maybe two.
>
> BTW, I would be very interested if anyone else has run into the missing
> THRE interrupt symptoms I've seen.
>
> Robert
>
> " 'Freedom' has no meaning of itself. There are always restrictions,
> be they legal, genetic, or physical. If you don't believe me, try to
> chew a radio signal. "
>
> Kelvin Throop, III





At 01:46 PM 7/28/04 +0000, you wrote:
>Hello all,
>
>I am puzzled by perhaps similar thing re: missing THRE int., FIFO empty?
>Can anyone plese help me to see what I do incorrectly?
>
>Polled UART0 works, INT on THRE doesn't.
>Timer0 ISR works, though.

Just a quick question, are you are sending are byte directly by writing it
to the THR before you expect to get a THRE interrupt (the transmission does
need to be primed)?

Robert

" 'Freedom' has no meaning of itself. There are always restrictions,
be they legal, genetic, or physical. If you don't believe me, try to
chew a radio signal. "

Kelvin Throop, III



void tx(char c)
{
UART0_THR = c;
}

..and then I expect INT (after the 8th bit is out).

--- In , Robert Adsett <subscriptions@a...> wrote:
> At 01:46 PM 7/28/04 +0000, you wrote:

> Just a quick question, are you are sending are byte directly by
writing it
> to the THR before you expect to get a THRE interrupt (the
transmission does
> need to be primed)?
>
> Robert
>
> " 'Freedom' has no meaning of itself. There are always restrictions,
> be they legal, genetic, or physical. If you don't believe me, try to
> chew a radio signal. "
>
> Kelvin Throop, III