Re: LPC2400 Dev board

Started by September 11, 2007

as far as I can see you don't have provided a CLKOUT connection from the LPC24xx to the FPGA. This would be very helpful for synchronous data transfer to/from FPGA. This clk signal should be feed to a pin of the fpga which can be routed to the internal PLL/DLL for a little time shift of the FPGA internal clock with respect to the clk signal the LPC will output at the pin.

This would speed up communication a lot with respect to an asynchronous data port which has to be sync'd in to the FPGA.

Having had a short glance on the user manual of the LPC so far it seems to me that it's possible to have CCLK on the CLKOUT pins all the time after configuring the right register bit. A 72 MHz clk signal seems to be fairly reasonable for the FPGA. You could generate other frequencies by using the PLL/DLL block inside the FPGA in addition.


An Engineer's Guide to the LPC2100 Series