can anyone tell me how to define the register value of I2SCLH &
I2SCLL , this is my first times to use the i2c, i read several sample
code about i2c but i still have no idea about these.
from data sheet (fCLK is the frequency of pclk.) does it means the
frequency of the crystal?
thanks
regards,
saidaiy
I2C question
Started by ●October 30, 2007
Reply by ●October 30, 20072007-10-30
--- In l..., "saidaiy" wrote:
>
> can anyone tell me how to define the register value of I2SCLH &
> I2SCLL , this is my first times to use the i2c, i read several sample
> code about i2c but i still have no idea about these.
>
> from data sheet (fCLK is the frequency of pclk.) does it means the
> frequency of the crystal?
>
> thanks
>
> regards,
> saidaiy
>
>From the LPC2148 User Manual section 11.7.8:
I2C Bit Frequency = PCLK / (I2CSCLH + I2CSCLL)
PCLK is whatever you set it to when you set up when you set up VPBDIV
but that is based on CCLK which is set to some multiple of the crystal
frequency when you set up PLL0.
So, maybe the crystal is 12 MHz and the PLL multiplies by 5 so CCLK is
60 MHz. Then maybe VPBDIV is set to divide by 4 (if that is what you
want; it can divide by 1, 2 or 4) so PCLK is 15 MHz.
Now, maybe you want 100 kHz for the I2C bit frequency (slow I2C) so:
100,000 = (15000000) / (I2CSCLH + I2CSCLL)
Then I2CSCLH + I2CSCLL = 15000000 / 100000 or 150.
Then is no reason the 2 values aren't the same so set them both for 75
to get 50% duty cycle on the clock. For a 400 kHz I2C, you need to
read the I2C spec to get the proper duty cycle. Google for it.
It all ties together but you have to start with crystal freq -> PLL
multiplication to get CCLK -> VPBDIV to get PCLK -> desired I2C clock
rate to get (I2CSCLH + I2CSCLL) -> I2C Spec to get the required duty
cycle if the I2C bit rate is not 100 kHz.
Richard
>
> can anyone tell me how to define the register value of I2SCLH &
> I2SCLL , this is my first times to use the i2c, i read several sample
> code about i2c but i still have no idea about these.
>
> from data sheet (fCLK is the frequency of pclk.) does it means the
> frequency of the crystal?
>
> thanks
>
> regards,
> saidaiy
>
>From the LPC2148 User Manual section 11.7.8:
I2C Bit Frequency = PCLK / (I2CSCLH + I2CSCLL)
PCLK is whatever you set it to when you set up when you set up VPBDIV
but that is based on CCLK which is set to some multiple of the crystal
frequency when you set up PLL0.
So, maybe the crystal is 12 MHz and the PLL multiplies by 5 so CCLK is
60 MHz. Then maybe VPBDIV is set to divide by 4 (if that is what you
want; it can divide by 1, 2 or 4) so PCLK is 15 MHz.
Now, maybe you want 100 kHz for the I2C bit frequency (slow I2C) so:
100,000 = (15000000) / (I2CSCLH + I2CSCLL)
Then I2CSCLH + I2CSCLL = 15000000 / 100000 or 150.
Then is no reason the 2 values aren't the same so set them both for 75
to get 50% duty cycle on the clock. For a 400 kHz I2C, you need to
read the I2C spec to get the proper duty cycle. Google for it.
It all ties together but you have to start with crystal freq -> PLL
multiplication to get CCLK -> VPBDIV to get PCLK -> desired I2C clock
rate to get (I2CSCLH + I2CSCLL) -> I2C Spec to get the required duty
cycle if the I2C bit rate is not 100 kHz.
Richard
Reply by ●December 5, 20082008-12-05
Setting the clock for I2C does not match what I read in the User Manual.
Based on my PCLK of 64Mhz when setting SCHL and SCLL to 0x50 I would
expect a clock with 50% duty cycle and 1.25us for low and high time.
But what I read with the scope is 2.3us low and 1.2us high.
Device: LPC2103
Clock: 16Mhz Oscillator
PLLCFG: 0x23 (MSEL=4, PSEL=2 => CCLK = 64Mhz)
APBDIV: 1 (PCLK = CCLK = 64MHz)
I am not having any problems using the I2C bus at all, no problems
writing to devices and reading from devices. All is running under
Interrupts based on some modified sample code from NXP. Just
questioning what is happening with my clock settings.
Pete
--- In l..., "rtstofer" wrote:
>
> --- In l..., "saidaiy" wrote:
> >
> > can anyone tell me how to define the register value of I2SCLH &
> > I2SCLL , this is my first times to use the i2c, i read several sample
> > code about i2c but i still have no idea about these.
> >
> > from data sheet (fCLK is the frequency of pclk.) does it means the
> > frequency of the crystal?
> >
> > thanks
> >
> > regards,
> > saidaiy
> > From the LPC2148 User Manual section 11.7.8:
>
> I2C Bit Frequency = PCLK / (I2CSCLH + I2CSCLL)
>
> PCLK is whatever you set it to when you set up when you set up VPBDIV
> but that is based on CCLK which is set to some multiple of the crystal
> frequency when you set up PLL0.
>
> So, maybe the crystal is 12 MHz and the PLL multiplies by 5 so CCLK is
> 60 MHz. Then maybe VPBDIV is set to divide by 4 (if that is what you
> want; it can divide by 1, 2 or 4) so PCLK is 15 MHz.
>
> Now, maybe you want 100 kHz for the I2C bit frequency (slow I2C) so:
>
> 100,000 = (15000000) / (I2CSCLH + I2CSCLL)
>
> Then I2CSCLH + I2CSCLL = 15000000 / 100000 or 150.
>
> Then is no reason the 2 values aren't the same so set them both for 75
> to get 50% duty cycle on the clock. For a 400 kHz I2C, you need to
> read the I2C spec to get the proper duty cycle. Google for it.
>
> It all ties together but you have to start with crystal freq -> PLL
> multiplication to get CCLK -> VPBDIV to get PCLK -> desired I2C clock
> rate to get (I2CSCLH + I2CSCLL) -> I2C Spec to get the required duty
> cycle if the I2C bit rate is not 100 kHz.
>
> Richard
>
Based on my PCLK of 64Mhz when setting SCHL and SCLL to 0x50 I would
expect a clock with 50% duty cycle and 1.25us for low and high time.
But what I read with the scope is 2.3us low and 1.2us high.
Device: LPC2103
Clock: 16Mhz Oscillator
PLLCFG: 0x23 (MSEL=4, PSEL=2 => CCLK = 64Mhz)
APBDIV: 1 (PCLK = CCLK = 64MHz)
I am not having any problems using the I2C bus at all, no problems
writing to devices and reading from devices. All is running under
Interrupts based on some modified sample code from NXP. Just
questioning what is happening with my clock settings.
Pete
--- In l..., "rtstofer" wrote:
>
> --- In l..., "saidaiy" wrote:
> >
> > can anyone tell me how to define the register value of I2SCLH &
> > I2SCLL , this is my first times to use the i2c, i read several sample
> > code about i2c but i still have no idea about these.
> >
> > from data sheet (fCLK is the frequency of pclk.) does it means the
> > frequency of the crystal?
> >
> > thanks
> >
> > regards,
> > saidaiy
> > From the LPC2148 User Manual section 11.7.8:
>
> I2C Bit Frequency = PCLK / (I2CSCLH + I2CSCLL)
>
> PCLK is whatever you set it to when you set up when you set up VPBDIV
> but that is based on CCLK which is set to some multiple of the crystal
> frequency when you set up PLL0.
>
> So, maybe the crystal is 12 MHz and the PLL multiplies by 5 so CCLK is
> 60 MHz. Then maybe VPBDIV is set to divide by 4 (if that is what you
> want; it can divide by 1, 2 or 4) so PCLK is 15 MHz.
>
> Now, maybe you want 100 kHz for the I2C bit frequency (slow I2C) so:
>
> 100,000 = (15000000) / (I2CSCLH + I2CSCLL)
>
> Then I2CSCLH + I2CSCLL = 15000000 / 100000 or 150.
>
> Then is no reason the 2 values aren't the same so set them both for 75
> to get 50% duty cycle on the clock. For a 400 kHz I2C, you need to
> read the I2C spec to get the proper duty cycle. Google for it.
>
> It all ties together but you have to start with crystal freq -> PLL
> multiplication to get CCLK -> VPBDIV to get PCLK -> desired I2C clock
> rate to get (I2CSCLH + I2CSCLL) -> I2C Spec to get the required duty
> cycle if the I2C bit rate is not 100 kHz.
>
> Richard
>
Reply by ●December 5, 20082008-12-05
To answer my own questions.
What I was seeing with the scope on the clock line was caused by some
I2C slave stretching the clock.
When no Slave is on the bus - the clock line behaves just as the good
book says it should.
Pete
--- In l..., "Peter Hofmann" wrote:
>
> Setting the clock for I2C does not match what I read in the User Manual.
>
> Based on my PCLK of 64Mhz when setting SCHL and SCLL to 0x50 I would
> expect a clock with 50% duty cycle and 1.25us for low and high time.
> But what I read with the scope is 2.3us low and 1.2us high.
>
> Device: LPC2103
> Clock: 16Mhz Oscillator
> PLLCFG: 0x23 (MSEL=4, PSEL=2 => CCLK = 64Mhz)
> APBDIV: 1 (PCLK = CCLK = 64MHz)
> I am not having any problems using the I2C bus at all, no problems
> writing to devices and reading from devices. All is running under
> Interrupts based on some modified sample code from NXP. Just
> questioning what is happening with my clock settings.
> Pete
> --- In l..., "rtstofer" wrote:
> >
> > --- In l..., "saidaiy" wrote:
> > >
> > > can anyone tell me how to define the register value of I2SCLH &
> > > I2SCLL , this is my first times to use the i2c, i read several
sample
> > > code about i2c but i still have no idea about these.
> > >
> > > from data sheet (fCLK is the frequency of pclk.) does it means the
> > > frequency of the crystal?
> > >
> > > thanks
> > >
> > > regards,
> > > saidaiy
> > >
> >
> > From the LPC2148 User Manual section 11.7.8:
> >
> > I2C Bit Frequency = PCLK / (I2CSCLH + I2CSCLL)
> >
> > PCLK is whatever you set it to when you set up when you set up VPBDIV
> > but that is based on CCLK which is set to some multiple of the crystal
> > frequency when you set up PLL0.
> >
> > So, maybe the crystal is 12 MHz and the PLL multiplies by 5 so CCLK is
> > 60 MHz. Then maybe VPBDIV is set to divide by 4 (if that is what you
> > want; it can divide by 1, 2 or 4) so PCLK is 15 MHz.
> >
> > Now, maybe you want 100 kHz for the I2C bit frequency (slow I2C) so:
> >
> > 100,000 = (15000000) / (I2CSCLH + I2CSCLL)
> >
> > Then I2CSCLH + I2CSCLL = 15000000 / 100000 or 150.
> >
> > Then is no reason the 2 values aren't the same so set them both for 75
> > to get 50% duty cycle on the clock. For a 400 kHz I2C, you need to
> > read the I2C spec to get the proper duty cycle. Google for it.
> >
> > It all ties together but you have to start with crystal freq -> PLL
> > multiplication to get CCLK -> VPBDIV to get PCLK -> desired I2C clock
> > rate to get (I2CSCLH + I2CSCLL) -> I2C Spec to get the required duty
> > cycle if the I2C bit rate is not 100 kHz.
> >
> > Richard
>
What I was seeing with the scope on the clock line was caused by some
I2C slave stretching the clock.
When no Slave is on the bus - the clock line behaves just as the good
book says it should.
Pete
--- In l..., "Peter Hofmann" wrote:
>
> Setting the clock for I2C does not match what I read in the User Manual.
>
> Based on my PCLK of 64Mhz when setting SCHL and SCLL to 0x50 I would
> expect a clock with 50% duty cycle and 1.25us for low and high time.
> But what I read with the scope is 2.3us low and 1.2us high.
>
> Device: LPC2103
> Clock: 16Mhz Oscillator
> PLLCFG: 0x23 (MSEL=4, PSEL=2 => CCLK = 64Mhz)
> APBDIV: 1 (PCLK = CCLK = 64MHz)
> I am not having any problems using the I2C bus at all, no problems
> writing to devices and reading from devices. All is running under
> Interrupts based on some modified sample code from NXP. Just
> questioning what is happening with my clock settings.
> Pete
> --- In l..., "rtstofer" wrote:
> >
> > --- In l..., "saidaiy" wrote:
> > >
> > > can anyone tell me how to define the register value of I2SCLH &
> > > I2SCLL , this is my first times to use the i2c, i read several
sample
> > > code about i2c but i still have no idea about these.
> > >
> > > from data sheet (fCLK is the frequency of pclk.) does it means the
> > > frequency of the crystal?
> > >
> > > thanks
> > >
> > > regards,
> > > saidaiy
> > >
> >
> > From the LPC2148 User Manual section 11.7.8:
> >
> > I2C Bit Frequency = PCLK / (I2CSCLH + I2CSCLL)
> >
> > PCLK is whatever you set it to when you set up when you set up VPBDIV
> > but that is based on CCLK which is set to some multiple of the crystal
> > frequency when you set up PLL0.
> >
> > So, maybe the crystal is 12 MHz and the PLL multiplies by 5 so CCLK is
> > 60 MHz. Then maybe VPBDIV is set to divide by 4 (if that is what you
> > want; it can divide by 1, 2 or 4) so PCLK is 15 MHz.
> >
> > Now, maybe you want 100 kHz for the I2C bit frequency (slow I2C) so:
> >
> > 100,000 = (15000000) / (I2CSCLH + I2CSCLL)
> >
> > Then I2CSCLH + I2CSCLL = 15000000 / 100000 or 150.
> >
> > Then is no reason the 2 values aren't the same so set them both for 75
> > to get 50% duty cycle on the clock. For a 400 kHz I2C, you need to
> > read the I2C spec to get the proper duty cycle. Google for it.
> >
> > It all ties together but you have to start with crystal freq -> PLL
> > multiplication to get CCLK -> VPBDIV to get PCLK -> desired I2C clock
> > rate to get (I2CSCLH + I2CSCLL) -> I2C Spec to get the required duty
> > cycle if the I2C bit rate is not 100 kHz.
> >
> > Richard
>
