I use LPC2378 with the mini bus. Because the software was written when
only rev '-' was available I had to access the external FPGA (8 bit
wide) with the GPIO pins. And this worked OK.
Now I have the revision A and tried to use the EMI. I tried several
configurations but had problems to access the 8 bit periphery.
BLS0 is used as write strobe. When I write a single byte I get 4 write
strobes and the FPGA FIFO doesn't like this behaviour. It seems that
only 32 bit words can be written in one block, but that's not what I want.
Does somebody use the EMI in a similar way?

thanks

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I don't believe there is anything anyone can do for you right now. It
seems that this is a quirk in the chip itself currently, this issue is
even stated clearly in the EMC section of the manual.

Exert from User's Manual:

To eliminate the possibility of endianness problems, all data transfers to
and from the
registers of the EMC must be 32 bits wide.
Note: If an access is attempted with a size other than a word (32 bits),
it causes an
ERROR response to the AHB bus and the transfer is terminated.
I'm pretty sure you'll have to use GPIO's to do the work and simulate your
needs in software. To me this is a mistake on NXP's side and restricts the
range of applications this chip can be used for.

Good Luck.


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Hi!

I am using EMC with LPC2378. First there is config of IO and EMC:

PINSEL6 = 0x00005555; // D0 ... D7
PINSEL8 = 0x55555555; // A0 ... A15
PINSEL9 = 0x50090000; // CS0, CS1, OE, BLS0
PCONP |= 0x00000800; // Turn On EMC PCLK

then, I use it in very simple, 8-bit way, 128k addressing with CS1/CS0

*Write:*
void emc_write(DWORD adr, BYTE val)
{
volatile BYTE *wr_ptr;
if (adr>0x0000ffff) adr += 0x01000000; // CS1
wr_ptr = (BYTE *)(EMC_BASE + adr);
*wr_ptr = val;
}

*Read:*
BYTE emc_read(DWORD adr)
{
volatile BYTE *wr_ptr;
if (adr>0x0000ffff) adr += 0x01000000; // CS1
wr_ptr = (BYTE *)(EMC_BASE + adr);
return *wr_ptr;
}
Hope this helps :)

BR,
Marko

m...@governors-america.com pravi:
> I don't believe there is anything anyone can do for you right now. It
> seems that this is a quirk in the chip itself currently, this issue is
> even stated clearly in the EMC section of the manual.
>
> Exert from User's Manual:
>
> To eliminate the possibility of endianness problems, all data transfers to
> and from the
> registers of the EMC must be 32 bits wide.
> Note: If an access is attempted with a size other than a word (32 bits),
> it causes an
> ERROR response to the AHB bus and the transfer is terminated.
> I'm pretty sure you'll have to use GPIO's to do the work and simulate your
> needs in software. To me this is a mistake on NXP's side and restricts the
> range of applications this chip can be used for.
>
> Good Luck.
>
>
>
>

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Thanks for your answers,

I guess that it's not possible like Mike explained, but I wonder that
the solution of Marko works (or, there are 4 accesses and data is
overwritten with the last access and nobody finds out).

What I did (and that didn't work because the KAKADU FPGA works with
FIFO and 4 accesses are the dead of FIFOs):

I used a macro:
#define KAKADU_WR_DATA (*(voilatile unsigned char*)(KAKADU_WR_ADDR))
#define KAKADU_RD_DATA (*(voilatile unsigned char*)(KAKADU_RD_ADDR))

example in my functions:

KAKADU_WR_DATA = 0x80; /* write */
var8 = KAKADU_RD_DATA; /* get data */

I don't see any difference between this solution and Markos suggestion
except that I don't use functions to save time.

Probably Mike is right and the EMI is unusable for only 8 bit transfers.

Specky
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--- In l..., Marko Pavlin wrote:
>
> Hi!
>
> I am using EMC with LPC2378. First there is config of IO and EMC:
>
> PINSEL6 = 0x00005555; // D0 ... D7
> PINSEL8 = 0x55555555; // A0 ... A15
> PINSEL9 = 0x50090000; // CS0, CS1, OE, BLS0
> PCONP |= 0x00000800; // Turn On EMC PCLK
>
> then, I use it in very simple, 8-bit way, 128k addressing with
CS1/CS0
>
> *Write:*
> void emc_write(DWORD adr, BYTE val)
> {
> volatile BYTE *wr_ptr;
> if (adr>0x0000ffff) adr += 0x01000000; // CS1
> wr_ptr = (BYTE *)(EMC_BASE + adr);
> *wr_ptr = val;
> }
>
> *Read:*
> BYTE emc_read(DWORD adr)
> {
> volatile BYTE *wr_ptr;
> if (adr>0x0000ffff) adr += 0x01000000; // CS1
> wr_ptr = (BYTE *)(EMC_BASE + adr);
> return *wr_ptr;
> }
> Hope this helps :)
>
> BR,
> Marko
>
> mfrazier@... pravi:
> > I don't believe there is anything anyone can do for you right
now. It
> > seems that this is a quirk in the chip itself currently, this
issue is
> > even stated clearly in the EMC section of the manual.
> >
> > Exert from User's Manual:
> >
> > To eliminate the possibility of endianness problems, all data
transfers to
> > and from the
> > registers of the EMC must be 32 bits wide.
> > Note: If an access is attempted with a size other than a word (32
bits),
> > it causes an
> > ERROR response to the AHB bus and the transfer is terminated.
> >
> >
> > I'm pretty sure you'll have to use GPIO's to do the work and
simulate your
> > needs in software. To me this is a mistake on NXP's side and
restricts the
> > range of applications this chip can be used for.
> >
> > Good Luck.
> >
> >
> >
> >
>
>
I was going to pick this part based on the ability to access external
byte-wide memory. When I read the EMC section in the manual I
thought "all data transfers to and from the registers of the EMC must
be 32 bits wide" was referring to only the EMC registers, not
accessing the memory! Are you sure about this?

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