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Uart 1 problem in LPC2103

Started by ahmedfarazvit December 6, 2008
Hi all,

The problem seems to be with the fractional divider registers of
UART1. I have configured UART0 and UART1 for 9600bps with and without
fractional divider registers. The baud rate matches for both UARTs
when there is no fractional divider used.

In configuration 1, I have taken MUL = 15 and DIV = 13 so that
fractional division factor is less than 1.
In configuration 2, I have moved the default value to FDR register
i.e. 0x10.

Please find below both the configurations :
Configuration 1 with Fraction Divider registers

For UART0:

PINSEL0 |= 0x00000005; //select uart0 tx and rx

// Enable Divisor latch bit
U0LCR = 0x83; // 8 Bit Data No Parity 1 Stop Bit

U0DLL = 42; // Baud rate fixed to 9600 @ PCLK = 12
Mhz, Error=0.16%

U0DLM = 0;
U0FDR = 0xFD; // Multiplier = 15, Divisor = 13

// Disable Divisor latch bit
U0LCR = 0x03;

// Enable and clear FIFO's
U0FCR = 0x07;

For UART1:

PINSEL0 |= 0x00050000; //select uart0 tx and rx
// Enable Divisor latch bit
U1LCR = 0x83; // 8 Bit Data No Parity 1 Stop Bit

U1DLL = 42; // Baud rate fixed to 9600 @ PCLK = 12
Mhz, Error=0.16%

U1DLM = 0;
U1FDR = 0xFD; // Multiplier = 15, Divisor = 13
// Disable Divisor latch bit
U1LCR = 0x03;
// Enable and clear FIFO's
U1FCR = 0x07;

Actual Baud Rate achieved :

UART 0 = 9615 bps
UART 1 = 17857 bps

Configuration 2 without Fraction Divider registers

For UART0:

PINSEL0 |= 0x00000005; //select uart0 tx and rx
// Enable Divisor latch bit
U0LCR = 0x83; // 8 Bit Data No Parity 1 Stop Bit

U0DLL = 78; // Baud rate fixed to 9600 @ PCLK = 12 Mhz,
Error=0.16%

U0DLM = 0;

U0FDR = 0x10; // Multiplier = 1, Divisor = 0
Clearing the FDR register

// Disable Divisor latch bit
U0LCR = 0x03;
// Enable and clear FIFO's
U0FCR = 0x07;

For UART1:

PINSEL0 |= 0x00050000; //select uart0 tx and rx
// Enable Divisor latch bit
U1LCR = 0x83; // 8 Bit Data No Parity 1 Stop Bit

U1DLL = 78; // Baud rate fixed to 9600 @ PCLK = 12
Mhz, Error=0.16%

U1DLM = 0;

U0FDR = 0x10; // Multiplier = 1, Divisor = 0
Clearing the FDR register

// Disable Divisor latch bit
U1LCR = 0x03;
// Enable and clear FIFO's
U1FCR = 0x07;

Actual Baud Rate achieved :

UART 0 = 9615 bps
UART 1 = 9615 bps
The inference what I think is that there is a problem with the baud
rate fractional divider registers for UART1.

Please let me know your comments\queries

Thanks,
Faraz.

An Engineer's Guide to the LPC2100 Series