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AutoBaud

Started by Bruce Paterson January 16, 2009
Hi,

I know this topic has been mentioned a couple of times, but I can't
recall an outcome.

Anyway, I'm trying to get autobauding going on an lpc2468 Uart1

I am using the fractional divider too (it's also a USB app), but the
manual implies that's all OK, and it uses the prescaled PCLK for it's
autobauding rather than the raw value.

In my case the prescaler is effectively 0.737, and the UART subsystem
clock divider is 8, so with 72MHz CPU clock the PCLK = 9MHz * 0.737

I set U1ACR to 0x305 (also tried 0x307 to try Mode 1 but no help).

If I don't get an "A" or an "a", or I get a receive error, I throw it
back into autobauding with U1ACR=0x305 again.

For 19.2k I expect U1DLL to be 22, and U1DLM to be 0.

What I get after typing in an "a" at 19.2k is U1DLL#6, U1DLM=7 (with
ACR= 4 indicating it's autobauded). That's a divider of 2028 !!

Any idea what's going on ?

Cheers,

Bruce


An Engineer's Guide to the LPC2100 Series

Outcome of Autobaud investigation

You may recall the issue (see original below) I had using Uart autobaud
with the fractional prescaler.
First, the reading back of DLL/DLM was my stuff-up; I forgot to set the
DLAT latch bit to read them. Of course the autobaud still wasn't working
anyway. Once I did set the DLAT bit, I found that the DLL was being set
to the value it would be if the autobaud hardware ignored the contents
of the FDR register.

After a number of exchanges with NXP, they have admitted that this is
the case. Basically, if you need to use the fractional prescaler,
autobaud will not work for you. In my opinion this may be a silicon
bug.

The user manual is incorrect where it talks about "The rate measuring
counter will start counting pclk cycles optionally pre-scaled by the
fractional baud-rate generator". The autobaud hardware ignores the
prescaler, and always uses the raw PCLK to calculate the DLL/M divider
values.

The user manual is also incorrect where it states "Typically the
fractional baud-rate generator is disabled (DIVADDVAL = 0) during
auto-baud. However, if the fractional baud-rate generator is enabled
(DIVADDVAL > 0), it is going to impact the measuring of UART1 Rx pin
baud-rate".
The problem is that fractional value does *not* impact the measurement
of the baud-rate. Autobaud will come up with the same numbers in DLL/M
whatever you put in FDR.

Now, it is possible for your software to read back the DLL/M after the
autobaud has "succeeded", multiply these values by the fractional
prescale fraction and put them back again. This actually works and I've
tested it across a range of baudrates. Though this will work OK for
situations where multiple autobauding sync characters are sent, such as
"?????" for the serial bootloading, it will not work for Hayes AT
schemes that sync on the A, because by the time you have set the DL
correctly retrospectively, the A/a (and possibly more due to FIFO)
characters have already been lost and are unrecoverable.

So, in summary:
If you use any LPC device with USB (=> non baudrate compatible crystal),
you cannot expect the autobaud to work, except in some special
circumstances.

Special circumstances are:
i) There are multiple sync characters in your autobaud scheme (losing
first few doesn't matter).
ii) For some lower specific baud rates, it may be possible, with a
tolerant Uart at the other end, to get away without using the fractional
prescaler at all, in which case autobaud will work (approximately).

Hopefully NXP will release an errata and update the user manuals of all
devices since the lpc2148, because at the moment you could be excused
for thinking autobaud was still a supported feature !

Cheers,
Bruce

Hi,

I know this topic has been mentioned a couple of times, but I can't
recall an outcome.

Anyway, I'm trying to get autobauding going on an lpc2468 Uart1

I am using the fractional divider too (it's also a USB app), but the
manual implies that's all OK, and it uses the prescaled PCLK for it's
autobauding rather than the raw value.

In my case the prescaler is effectively 0.737, and the UART subsystem
clock divider is 8, so with 72MHz CPU clock the PCLK = 9MHz * 0.737

I set U1ACR to 0x305 (also tried 0x307 to try Mode 1 but no help).

If I don't get an "A" or an "a", or I get a receive error, I throw it
back into autobauding with U1ACR=0x305 again.

For 19.2k I expect U1DLL to be 22, and U1DLM to be 0.

What I get after typing in an "a" at 19.2k is U1DLL#6, U1DLM=7with
ACR= 4 indicating it's autobauded). That's a divider of 2028 !!

Any idea what's going on ?

Cheers,

Bruce