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how to set baudrate 38400 while PCLK is 60 MHz?

Started by yhb123 March 23, 2009
Hi all,

Has anyone successfully set the LPC2100 Baudrate 38400 while PCLK is 60MHz?
I set the LPC2148 with the following settings with Calculated Baudrate (BPS): 38412. Because a application uses LPC2148's USB port, 12 MHz crystal has to be used here. If FDR is not used, the baudrate 4800 and 9600 are working. But baudrate 38400 doesn't work even FDR is used.

PINSEL0 = 0x00000005;

U0LCR = 0x83; * 8 bits, no Parity, 1 Stop bit U0FDR = 131;
U0DLL = 71;
U0DLM = 0;
U0LCR = 0x03;

A PC program can not read the data correctly.

An Engineer's Guide to the LPC2100 Series

yhb123 wrote:
> Hi all,
>
> Has anyone successfully set the LPC2100 Baudrate 38400 while PCLK is
> 60MHz? I set the LPC2148 with the following settings with Calculated
> Baudrate (BPS): 38412. Because a application uses LPC2148's USB port,
> 12 MHz crystal has to be used here. If FDR is not used, the baudrate
> 4800 and 9600 are working. But baudrate 38400 doesn't work even FDR
> is used.
>
> PINSEL0 = 0x00000005;
>
> U0LCR = 0x83; * 8 bits, no Parity, 1 Stop bit
> U0FDR = 131; U0DLL = 71; U0DLM = 0; U0LCR = 0x03;
>
> A PC program can not read the data correctly.

I'm calculating a different divider: 60 MHz / (16 * 38400) = 97.65
When choosing a divider of 98, the error is smaller than 0.5% so
using the FDR isn't even needed.

Kind regards,
Bertrik
How do you get a PCLK of 60MHz? Do you mean the CPU CLK?
Normally PCLKu/4 which would be 15MHz.


HM2 wrote:
> How do you get a PCLK of 60MHz? Do you mean the CPU CLK?
> Normally PCLKu/4 which would be 15MHz.

Look up APBDIV in the user manual (sometimes called VPBDIV)

Bertrik
On Tue, 24 Mar 2009 08:34:55 +0100, you wrote:

>HM2 wrote:
>> How do you get a PCLK of 60MHz? Do you mean the CPU CLK?
>> Normally PCLKu/4 which would be 15MHz.

Why 'normally'.... ? Apart from apps that care about every bit of power draw,

On parts with fractional baudrate gens, 38K4 at 15MHz shouldn't be a problem - use NXP's baudrate
calculator spreadsheet to find suitable baud values
hello ,

1. cclk of 60MHZ is 15MHZ.
why because,VPBis total freq by 4.
VPB=60MHZ/4.
VPB =15 MHZ.

2.
for baud rateyou have to set diviser latch.

baud rate =cclk/(x*16).

x=cclk/(baudrate*16).

x= diviserlatch

if you will set this value to corsponding register you can get 9600 baudrate.

venu


--- On Tue, 24/3/09, Bertrik Sikken wrote:
From: Bertrik Sikken
Subject: Re: [lpc2000] how to set baudrate 38400 while PCLK is 60 MHz?
To: l...
Date: Tuesday, 24 March, 2009, 1:04 PM

HM2 wrote:
> How do you get a PCLK of 60MHz? Do you mean the CPU CLK?
> Normally PCLK=Fcpu/4 which would be 15MHz.

Look up APBDIV in the user manual (sometimes called VPBDIV)

Bertrik

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venu babu wrote:
> hello ,
>
> 1. cclk of 60MHZ is 15MHZ.
> why because, VPB is total freq by 4.
> VPB`MHZ/4.
> VPB MHZ.
>
> 2.
> for baud rate you have to set diviser latch.
>
> baud rate k/(x*16).
>
> xk/(baudrate*16).
>
> x= diviserlatch
>
> if you will set this value to corsponding register you can get 9600 baudrate.

The subject says PCLK is 60 MHz, not 15 MHz.

To reach a PCLK of 60 MHz, I recommend you
Look up APBDIV in the user manual (sometimes called VPBDIV)

Using a higher PCLK than the default setting of CCLK/4 can help with
other peripherals too, to increase the accuracy or the absolute speed
(e.g. with a PCLK of 15 MHz, you can reach only 7.5 Mbit/s SPI
communication).

Kind regards,
Bertrik