I'm having a problem with the SPI bus and am wondering if anyone else has
encountered similar problems.
The problems is that the SPI Slave fails to interrupt when a byte is sent
from the SPI Master.
* 2x LPC2210.
* SPI 0 from 2210-0 is wired to SPI 1 on 2210-1 and SPI 0 from 2210-1
is wired to SPI 1 on 2210-0.
* SPI 0 is Master and SPI 1 is Slave in both cases.
* SPI clk is 1041666 bps (fails at slower clock speed also - tried
down to 100806 bps)
* Enabled interrupts SPI 0, SPI 1, UART 1, TMR 0 (all irq - fiq not
* Interrupt priority: 0-SPI 1, 1-TMR 0, 2-UART 1, 3-SPI 0
* All four SPI peripherals are active (bi-directional transfer)
Observed condition at failure:
SPI 1 has SPINT bit set. VIC shows interrupt channel 11 and channel 4
active in the IRQStatus register. VicVecAddr contains the address for
channel 11 (SPI 1). No vectoring occurs. If a '1' is written to
S1SPINT_bit.SPIINT the interrupt is taken and processing continues. No
overrun conditions are detected when this conditin exists (the SPI 0 Master
does not send another byte until the interrupt indicating the previous byte
is sent occurs).
As a work-around I have implemented a poll routine that queries the
S1SPINT_bit.SPIINT bit every 10 Ms. If it is found to be on a one is
written to it. This seems to clear up the hang condition and processing
continues normally. This is not a good final solution because 1) it
requires CPU cycles to poll and 2) is greatly slows data transfers on the
At 05:32 PM 12/6/04 -0600, you wrote:|
>I'm having a problem with the SPI bus and am wondering if anyone else has
>encountered similar problems.
>The problems is that the SPI Slave fails to interrupt when a byte is sent
>from the SPI Master.
Have you read the SPI errata note?
" 'Freedom' has no meaning of itself. There are always restrictions,
be they legal, genetic, or physical. If you don't believe me, try to
chew a radio signal. "
Kelvin Throop, III