Does the 1768 have any sort of Transmission Complete interrupt? I see that there is a flag (TEMT) in the UART Line Status Register, but it doesn't appear to trip an interrupt. I wanted to make sure I searched for everything before implimenting a polling solution for identifying transmissions being complete.

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Hello Ron,

Monday, February 8, 2010, 9:12:26 PM, you wrote:

R> Does the 1768 have any sort of Transmission Complete interrupt? I
R> see that there is a flag (TEMT) in the UART Line Status Register,
R> but it doesn't appear to trip an interrupt. I wanted to make sure
R> I searched for everything before implimenting a polling solution
R> for identifying transmissions being complete.

(from UM10360 Rev. 01 4 January 2010)

Table 50.
Connection of interrupt sources to the Vectored Interrupt Controller
Interrupt ID Exception Number Vector Offset Function
5 21 0x54 UART0
Flag(s)
...
Transmit Holding Register Empty (THRE)
...

Chapter 14: LPC17xx UART0/2/3
1. Basic configuration
...
6. Interrupts: To enable UART interrupts set bit DLAB =0 in register U0/2/3LCR
(Table 14278). This enables access to U0/2/3IER (Table 14274). Interrupts are
enabled in the NVIC using the appropriate Interrupt Set Enable register.

4.4 UARTn Interrupt Enable Register

Bit 1 THRE Interrupt Enable
Enables the THRE interrupt for UARTn. The status of this can be read
from UnLSR[5].
0 Disable the THRE interrupts.
1 Enable the THRE interrupts.

So I guess you should do the following:

1) Set DLAB (UnLCR[7]) to 0
2) Set UnIER[1] = 1
3) Ebable UARTn interrupt on NVIC
4) In the handler, check UnIIR[3:1] (IntId) == 001 or UnLSR[5]==1 to detect THRE condition.

As alternative you can use DMA which also has interrupts on the end-of-transfer condition.

--
WBR,
Igor mailto:s...@mail.ru

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