LPC2103 loses JTAG with bad PLL setup?
I have an LPC2103 and my bootup code sets the MAM and PLL. The thing is, I
must have set it incorrectly because I cannot seem to get my Olimex to connect
to it anymore.
12MHz crystal, PLL set to 60MHz with M=4 P=1 (0x24). MAM set to 4.
My openocd configuration for the LPC2103 and Olimex was one I'd taken from the
# LPC2000 -> SRST causes TRST
reset_config trst_and_srst srst_pulls_trst
# reset delays
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id
set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position
$_TARGETNAME -variant arm7tdmi-s_r4
Before I'd made the PLL change the Olimex had no problem whatsoever, but now
it seems like the chip is just not able to talk to the Olimex through JTAG
(weird values coming back, communication failures, CPSR invalid data, etc.)
Short of removing the crystal and installing a slower one, is there something
I can do to try to get the chip to respond?
> Short of removing the crystal and installing a slower one, is there
> something I can do to try to get the chip to respond?
Forcing bootloader mode (P0.14 held low while resetting) helped, but it was
still a bear to get control over the LPC2103 with JTAG.
12MHz crystal, M=4, P=1 (0x24) sets the PLL to 60MHz, does it not? MAM timing
is set to 4 as well, which should be right.
I have two different boards where I can't get to the higher clock frequencies,
this one and another with a 13MHz crystal where I'm using the same PLL
settings for 65MHz.
If I run through the calculations for 12MHz and M=4, P=1:
CCLK = 12MHz * 5 = 60MHz
Fcco = 60MHz * 2 * 2 = 240MHz
Those values are within the specifications (70MHz CCLK, 156 - 320MHz Fcco), but
the device doesn't work.
Similarly for 13MHz and M=4, P=1:
CCLK = 13MHz * 5 = 65MHz
Fcco = 65MHz * 2 * 2 = 260MHz
Can anyone shed some light on why these values aren't working for the LPC2103?
My MAM/PLL setting code looks fine to me.
/* Set up the MAM */
ldr r0, =0xe01fc000 /* MAM base register */
mov r1, #0x00
str r1, [r0] /* Disable MAM */
mov r1, #0x04
str r1, [r0, #0x04] /* set MAM timing */
mov r1, #0x02
str r1, [r0] /* Enable MAM */
/* Set up the PLL. 13MHz oscillator input */
ldr r0, =0xe01fc080 /* PLL base register */
mov r3, #0x24 /* 65MHz: M=4, P=1 */
str r3, [r0, #0x04] /* set PLLCFG */
mov r3, #0x01
str r3, [r0] /* enable PLL */
mov r1, #0xaa
mov r2, #0x55
str r1, [r0, #0x0c] /* tickle PLLFEED */
str r2, [r0, #0x0c]
ldr r3, [r0, #0x08]
ands r3, r3, #(1 << 10)
beq pll_loop /* loop until PLL locked */
mov r3, #0x03
str r3, [r0] /* enable and use PLL clock */
str r1, [r0, #0x0c]
str r2, [r0, #0x0c]