reference:
using the LPC2468 processor with a 12mhz crystal, and cclk = 72Mhz, Keil rtos
-the 72Mhz is max system clock for the LPC2468
-there is next to no information on the DAC, does the thing work as expected?

main question:
what is a peripheral clock devisor for DAC in register PCLKSEL0.PCLK_DAC for max rate. what is the max expected frequency after the division of PCLKSEL0.PCLK_DAC?

Thanks everyone!

Start a New Thread

any document in mind for the Table 58?

the nxp users manual ipc23xxx.prf UM10211 shows:
"Table 58. Pad interface and control signal descriptions"

---------------

--- In l..., Timo wrote:
>
> On 09/28/2010 07:06 PM, gsxr750jah wrote:
> > main question:
> > what is a peripheral clock devisor for DAC in register PCLKSEL0.PCLK_DAC
> > for max rate. what is the max expected frequency after the division of
> > PCLKSEL0.PCLK_DAC?
>
> Doesn't table 58 say it all?
>
> --
>
> Timo
>

Start a New Thread

gsxr750jah wrote:
> any document in mind for the Table 58?
>
> the nxp users manual ipc23xxx.prf UM10211 shows:
> "Table 58. Pad interface and control signal descriptions"

But you said you are using LPC2468. See "Table 58. Peripheral Clock Selection
register bit values" in LPC24XX UM10237 Rev. 04 - 26 August 2009 - that's the
latest.

--

Timo

Start a New Thread

my bad not referencing the lpc24xx.pdf
thanks!
--- In l..., tike64@... wrote:
>
> gsxr750jah wrote:
> > any document in mind for the Table 58?
> >
> > the nxp users manual ipc23xxx.prf UM10211 shows:
> > "Table 58. Pad interface and control signal descriptions"
>
> But you said you are using LPC2468. See "Table 58. Peripheral Clock Selection
> register bit values" in LPC24XX UM10237 Rev. 04 - 26 August 2009 - that's the
> latest.
>
> --
>
> Timo
>

Start a New Thread