Good afternoon, everyone,
I have an LPC2103 set up to receive data as an SSP slave. I am running at a
CCLK/PCLK of 60MHz (16MHz with PLL bringing me up to 60MHz). I've verified
that
the PLL is connected and at the correct settings. I've also verified that
PCLK
is at 1:1 to CCLK and that the MAM is set up correctly.
I am having no trouble with SSP clocks up to about 2MHz, but I'm really
hoping
to hit a lot closer to 30MHz.
The code is really simple right now. The main loop just spins (does nothing)
and the SSP interrupt handler toggles a pin to show when it's received
data.
The pin toggle is always the same distance from the frame sync signal at
slower clocks, but as I start going above 2MHz the point that I get the
interrupt starts to jump around; it jumps by exactly one SSP clock bit time,
leading me to believe that the hardware is missing clocks as I increase speed.
If I continue to increase the speed it will jump by two, three, four bit
times. The oscilloscope's accumulate mode shows that it's always an
integer
number of SSP bit times that the pin toggles on.
Now the datasheet shows that the SSP can run up to 30MHz, and looking around
on the 'net (including this list) shows that people are running at least
into
the teens of MHz, but everyone's talking about master mode. I'm
running in
slave mode and I'm wondering if the SSP has some other constraints which
limit
the maximum slave clock frequency.
Has anyone run the SSP in slave mode at high frequency? Are there different
maximum frequencies for master and slave SSP modes?
Regards,
Andrew
LPC2103 SSP slave - max clock?
Started by ●October 6, 2010
Reply by ●October 6, 20102010-10-06
--- In l..., "Andrew Kohlsmith (mailing lists account)" wrote:
>
> Good afternoon, everyone,
>
> I have an LPC2103 set up to receive data as an SSP slave. I am running at a
> CCLK/PCLK of 60MHz (16MHz with PLL bringing me up to 60MHz). I've verified that
> the PLL is connected and at the correct settings. I've also verified that PCLK
> is at 1:1 to CCLK and that the MAM is set up correctly.
>
> I am having no trouble with SSP clocks up to about 2MHz, but I'm really hoping
> to hit a lot closer to 30MHz.
Look at section 4.5 of the User Manual. Apparently, you have to set the SSP prescale divider to at least 12 in slave mode. It would seem to me that this will limit the speed of SSP while in that mode.
Look at table 149 (SCR bits) where they show that you will be limited to 60 MHz divided by 12 or 5 MHz in slave mode.
Richard
>
> Good afternoon, everyone,
>
> I have an LPC2103 set up to receive data as an SSP slave. I am running at a
> CCLK/PCLK of 60MHz (16MHz with PLL bringing me up to 60MHz). I've verified that
> the PLL is connected and at the correct settings. I've also verified that PCLK
> is at 1:1 to CCLK and that the MAM is set up correctly.
>
> I am having no trouble with SSP clocks up to about 2MHz, but I'm really hoping
> to hit a lot closer to 30MHz.
Look at section 4.5 of the User Manual. Apparently, you have to set the SSP prescale divider to at least 12 in slave mode. It would seem to me that this will limit the speed of SSP while in that mode.
Look at table 149 (SCR bits) where they show that you will be limited to 60 MHz divided by 12 or 5 MHz in slave mode.
Richard
Reply by ●October 7, 20102010-10-07
On Wednesday, October 06, 2010 09:54:00 pm you wrote:
> Look at section 4.5 of the User Manual. Apparently, you have to set the
> SSP prescale divider to at least 12 in slave mode. It would seem to me
> that this will limit the speed of SSP while in that mode.
Gah, I can't believe I missed that. I've been running with it unconfigured
(it's a receive-only SSP peripheral) -- adjusting SSPCPSR doesn't seem to
affect reception at all, and it does seem to be limited to 1/12 PCLK.
Thank you very much for pointing this out to me. It looks like the current rev
will have a limit on frequency and I'll be looking for a replacement processor
to handle up to 50MHz input clock.
I think before I go that far though I will attempt to get faster by bit-
banging the SSP reception. It's been a while since I've dived into ARM
assembly. :-)
-A.
> Look at section 4.5 of the User Manual. Apparently, you have to set the
> SSP prescale divider to at least 12 in slave mode. It would seem to me
> that this will limit the speed of SSP while in that mode.
Gah, I can't believe I missed that. I've been running with it unconfigured
(it's a receive-only SSP peripheral) -- adjusting SSPCPSR doesn't seem to
affect reception at all, and it does seem to be limited to 1/12 PCLK.
Thank you very much for pointing this out to me. It looks like the current rev
will have a limit on frequency and I'll be looking for a replacement processor
to handle up to 50MHz input clock.
I think before I go that far though I will attempt to get faster by bit-
banging the SSP reception. It's been a while since I've dived into ARM
assembly. :-)
-A.
