LPC3240 DMA issue

Started by Jean-Marc Colagrossi October 29, 2010
Hi all,

I am working on a new project using the LPC3240 controller. To communicate
with an external FPGA I use SSP0 with DMA.
The behavior observed with the oscilloscope looks fine as the data sent and
received are correct. The settings are :

data width = 16 bits. The upper 8 bits are FPGA commands, and the lower 8
bits are the FPGA answers.
data burst = no

What I observed with the oscilloscope is correct and looks like :

Data sent
....command1........................command2..........................command3........................command4............
Data observed
....................answer1...........................answer2...............................answer3............................answer4

But the issue is that, when I read the content of the memory I have :
Data sent
....command1........................command2..........................command3........................command4............
Data read in memory
....................randomData........................answer1...............................answer2............................answer3

It looks like the first data is the response of the last command sent of the
previous data transfer and it is blocked somewhere and comes out only on the
next data transfer. I already checked that the SSP FIFO buffer is empty
before starting the data transfer.

I don't understand what I missed.

Help will be very apreciated... ;-)

Regards

Jean-Marc

An Engineer's Guide to the LPC2100 Series

I think it is normal, common to all ssp controllers and is inherent on how the ssp works.
While the controller transmits the command, it is receiving the answer
at the same time.But the answer is available to the reception register only when the write operation is completed, then you can access at the next cycle.
You have to take in account this, trashing the first invalid data.
..and if you want to read the last answer, you have to add a dummy command at the end.

Carlo

--- In l..., Jean-Marc Colagrossi wrote:
>
> Hi all,
>
> I am working on a new project using the LPC3240 controller. To communicate
> with an external FPGA I use SSP0 with DMA.
> The behavior observed with the oscilloscope looks fine as the data sent and
> received are correct. The settings are :
>
> data width = 16 bits. The upper 8 bits are FPGA commands, and the lower 8
> bits are the FPGA answers.
> data burst = no
>
> What I observed with the oscilloscope is correct and looks like :
>
> Data sent
> ....command1........................command2..........................command3........................command4............
> Data observed
> ....................answer1...........................answer2...............................answer3............................answer4
>
> But the issue is that, when I read the content of the memory I have :
> Data sent
> ....command1........................command2..........................command3........................command4............
> Data read in memory
> ....................randomData........................answer1...............................answer2............................answer3
>
> It looks like the first data is the response of the last command sent of the
> previous data transfer and it is blocked somewhere and comes out only on the
> next data transfer. I already checked that the SSP FIFO buffer is empty
> before starting the data transfer.
>
> I don't understand what I missed.
>
> Help will be very apreciated... ;-)
>
> Regards
>
> Jean-Marc
>

Thanks Carlo for you answer,

But I have to say that I don't agree with you.

On the LPC3240 the SSP (Miso-Mosi-SCLK) are full duplex data transmission.

My FPGA is a 8 bits command width and 8 bits answer width. That means if I
send for example :
0xffff to Mosi -> I will have as answer 0x0002 on Miso. Means that in the
same time I sent 0xffff, the input fifo of the SPI is filled with 0x0002.
Then the DMA should transfer the data 0x0002 into the RAM because the FIFO
is not empty.

The data observed on the SPI bus are correct. But the data into RAM are not
!!! It looks like that I have a intermediate buffer between the FIFO of the
SPI and the RAM.

I have to note that It is working as I am expecting when I don't use DMA.

Regards,

Jean-Marc
Problem solved: [:D]
Hi all,
The Pseudo code was :
// Setup DMA channel for output data
set_canal_out_source_address();
set_canal_out_destination_address(); set_canal_out_linked_list();
set_canal_out_control(); set_canal_out_config_ch();
// Setup DMA channel for input data nop();
set_canal_in_source_address();
set_canal_in_destination_address(); set_canal_in_linked_list();
set_canal_in_control(); set_canal_in_config_ch();
Without the nop();
the data posted in my case are : 0xffff and 0xfeff. The expected answer
is : 0x0002, 0x0001. And the received answer was : randomValue, 0x0002,
0x0001 (I needed to send 3 byte to got the third byte - 0x0001 -).
With the nop();
the data posted in my case are : 0xffff and 0xfeff. The expected answer
is : 0x0002, 0x0001. And the received answer was : 0x0002, 0x0001.
I have to say that I am using a CrossConnect JTAG debbuger.
Witout the JTAG debbuger don't need the nop instruction. But with the
JTAG debbuger, I need the nop() instruction.

--- In l..., Jean-Marc Colagrossi
wrote:
>
> Thanks Carlo for you answer,
>
> But I have to say that I don't agree with you.
>
> On the LPC3240 the SSP (Miso-Mosi-SCLK) are full duplex data
transmission.
>
> My FPGA is a 8 bits command width and 8 bits answer width. That means
if I
> send for example :
> 0xffff to Mosi -> I will have as answer 0x0002 on Miso. Means that in
the
> same time I sent 0xffff, the input fifo of the SPI is filled with
0x0002.
> Then the DMA should transfer the data 0x0002 into the RAM because the
FIFO
> is not empty.
>
> The data observed on the SPI bus are correct. But the data into RAM
are not
> !!! It looks like that I have a intermediate buffer between the FIFO
of the
> SPI and the RAM.
>
> I have to note that It is working as I am expecting when I don't use
DMA.
>
> Regards,
>
> Jean-Marc
>