Hi

Below is the description of the CTCR register for PWM in 23xx, 24xx.

-----------------------

Table 486: PWM Count control Register (PWM1CTCR - address 0xE001 8004) bit description Bit Symbol Value Description Reset

1:0 Counter/Timer Mode

00 Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.

01 Counter Mode: the*TC is incremented on rising edges of the PCAP* input selected by bits 3:2.

10 Counter Mode: the*TC is incremented on falling edges of the PCAP* input selected by bits 3:2.

11 Counter Mode: the*TC is incremented on both edges of the PCAP* input selected by bits 3:2.

3:2 Count Input Select

When bits 1:0 of this register are not 00, these bits select which PCAP pin which carries the signal used to increment the TC.

00 PCAP1.0

01 CAP1.1 (Other combinations are reserved)

-------------------------------
I think that the description of the modes is wrong because in all three counter modes it says
*"TC is incremented on xx edges of the PCAP input"*,
but it should say that the prescale counter is incremented and according to the prescale register it increases TC on PR and PC match.

It is also the same with the timer CTCR description but there they have added a note that explains that point
*"This field selects which rising PCLK edges can increment Timers Prescale Counter (PC), or clear PC and increment Timer Counter (TC)"*

My point is that when I read the data sheet I expect to find a clear description of how things work and I feed that the PWM CTCR
description doesn't do that.
I already knew how the timer works and the description seemed strange so I tried in keil debugger to see how it really works
and as I thought the CAP pulses increase the prescale counter and then TC is incremented when the is a PR and PC match.

Alex

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Another strange thing I see is in the 23xx PWM capture control register (PWM CCR),
the 23xx have only two PWM capture inputs (PCAP0, PCAP1) but the CCR settings have options to capture or generate interrupt for n.0, n.1, n.2, n.3.
The same register in 24xx seems to be correct because it has options for n.0 and n.1 only and the rest are reserved.
Also the datasheet should say PCAPn.x which are connected to the PWM and not CAPn.x which are connected to the timer.
Am I wrong? (I haveUM10211/LPC23XX User manual/ )

Alex

On 04/30/2011 11:46 AM, Alex wrote:

> Hi
>
> Below is the description of the CTCR register for PWM in 23xx, 24xx.
>
> -----------------------
>
> Table 486: PWM Count control Register (PWM1CTCR - address 0xE001 8004) bit description Bit Symbol Value Description Reset
>
> 1:0 Counter/Timer Mode
>
> 00 Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.
>
> 01 Counter Mode: the*TC is incremented on rising edges of the PCAP* input selected by bits 3:2.
>
> 10 Counter Mode: the*TC is incremented on falling edges of the PCAP* input selected by bits 3:2.
>
> 11 Counter Mode: the*TC is incremented on both edges of the PCAP* input selected by bits 3:2.
>
> 3:2 Count Input Select
>
> When bits 1:0 of this register are not 00, these bits select which PCAP pin which carries the signal used to increment the TC.
>
> 00 PCAP1.0
>
> 01 CAP1.1 (Other combinations are reserved)
>
> -------------------------------
> I think that the description of the modes is wrong because in all three counter modes it says
> *"TC is incremented on xx edges of the PCAP input"*,
> but it should say that the prescale counter is incremented and according to the prescale register it increases TC on PR and PC match.
>
> It is also the same with the timer CTCR description but there they have added a note that explains that point
> *"This field selects which rising PCLK edges can increment Timers Prescale Counter (PC), or clear PC and increment Timer Counter (TC)"*
>
> My point is that when I read the data sheet I expect to find a clear description of how things work and I feed that the PWM CTCR
> description doesn't do that.
> I already knew how the timer works and the description seemed strange so I tried in keil debugger to see how it really works
> and as I thought the CAP pulses increase the prescale counter and then TC is incremented when the is a PR and PC match.
>
> Alex
>
> Start a New Thread

Can someone please verify if the correct number of capture registers in 23xx PWM is four as the datasheet says or if they are just two as I think.
I haven't found any 23xx mcu that has a PCAP2 or PCAP3 pin so I don' know if I should include the CCR settings for them but the datasheet
says that there are four capture registers and also has PWMxCCR register bits 6-11 to set them.
They either exist but can't be used of they are reserved (like in 24xx) and shouldn't be modified so the datasheet is wrong.

Alex

On 04/30/2011 01:05 PM, Alex wrote:

> Another strange thing I see is in the 23xx PWM capture control register (PWM CCR),
> the 23xx have only two PWM capture inputs (PCAP0, PCAP1) but the CCR settings have options to capture or generate interrupt for n.0, n.1, n.2, n.3.
> The same register in 24xx seems to be correct because it has options for n.0 and n.1 only and the rest are reserved.
> Also the datasheet should say PCAPn.x which are connected to the PWM and not CAPn.x which are connected to the timer.
> Am I wrong? (I haveUM10211/LPC23XX User manual/ )
>
> Alex
>
> On 04/30/2011 11:46 AM, Alex wrote:
>
>> Hi
>>
>> Below is the description of the CTCR register for PWM in 23xx, 24xx.
>>
>> -----------------------
>>
>> Table 486: PWM Count control Register (PWM1CTCR - address 0xE001 8004) bit description Bit Symbol Value Description Reset
>>
>> 1:0 Counter/Timer Mode
>>
>> 00 Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.
>>
>> 01 Counter Mode: the*TC is incremented on rising edges of the PCAP* input selected by bits 3:2.
>>
>> 10 Counter Mode: the*TC is incremented on falling edges of the PCAP* input selected by bits 3:2.
>>
>> 11 Counter Mode: the*TC is incremented on both edges of the PCAP* input selected by bits 3:2.
>>
>> 3:2 Count Input Select
>>
>> When bits 1:0 of this register are not 00, these bits select which PCAP pin which carries the signal used to increment the TC.
>>
>> 00 PCAP1.0
>>
>> 01 CAP1.1 (Other combinations are reserved)
>>
>> -------------------------------
>> I think that the description of the modes is wrong because in all three counter modes it says
>> *"TC is incremented on xx edges of the PCAP input"*,
>> but it should say that the prescale counter is incremented and according to the prescale register it increases TC on PR and PC match.
>>
>> It is also the same with the timer CTCR description but there they have added a note that explains that point
>> *"This field selects which rising PCLK edges can increment Timers Prescale Counter (PC), or clear PC and increment Timer Counter (TC)"*
>>
>> My point is that when I read the data sheet I expect to find a clear description of how things work and I feed that the PWM CTCR
>> description doesn't do that.
>> I already knew how the timer works and the description seemed strange so I tried in keil debugger to see how it really works
>> and as I thought the CAP pulses increase the prescale counter and then TC is incremented when the is a PR and PC match.
>>
>> Alex
>>
>> Start a New Thread