I have a problem with a LPC2468 board. I use Yargato on Eclipse and configured
everything as in the description. I changed an example for LPC series to fit the
LPC2468. (Amount of flash, ram and adresses)
Compiling is without any errors. When I start the GDB, the segger console
says:
Reading all registers
Read 4 bytes @ address 0x00000000 (Data = 0xE59FF018)
Target endianess set to "little endian"
JTAG speed set to 30 kHz
ERROR: PC of target system has unexpected value of 0x00000518 after reset.
Resetting target (SAM7 soft reset)
Sleep 10ms
Writing 0x00008000 @ address 0xFFFFFD44
Writing 0x00000601 @ address 0xFFFFFC20
Sleep 10ms
Writing 0x00480A0E @ address 0xFFFFFC2C
Sleep 10ms
Writing 0x00000007 @ address 0xFFFFFC30
Sleep 10ms
Writing 0x00480100 @ address 0xFFFFFF60
Sleep 100ms
JTAG speed set to 12000 kHz
Downloading 400 bytes @ address 0x00000000
ERROR: Write memory error @ address 0x00000000, word access: Core error.
Downloading 828 bytes @ address 0x00000190
WARNING: Failed to read cacheable memory @ address 0x00000000
Read 4 bytes @ address 0x00000000 (Data = 0x00000000)
I think there must be a problem in the linker file but I can't find it.
(it's my first time I work with startup and linker files, I just copied the
startup file and the linker file and didn't change much)
Maybe somebody has such files that are definetly running on this processor or
cann help me with it.
Problem with LPC2468 and GCC (or Segger J-Link)
Started by ●March 13, 2012
Reply by ●March 13, 20122012-03-13
Hi,
> I have a problem with a LPC2468 board. I use Yargato on Eclipse and
configured
> everything as in the description. I changed an example for LPC series to
fit
> the LPC2468. (Amount of flash, ram and adresses)
>
> Compiling is without any errors. When I start the GDB, the segger console
> says:
> Reading all registers
> Read 4 bytes @ address 0x00000000 (Data = 0xE59FF018) Target endianess set
to
> "little endian"
> JTAG speed set to 30 kHz
> ERROR: PC of target system has unexpected value of 0x00000518 after reset.
> Resetting target (SAM7 soft reset)
"SAM7 soft reset" on an LPC2468?
> Sleep 10ms
> Writing 0x00008000 @ address 0xFFFFFD44
> Writing 0x00000601 @ address 0xFFFFFC20
> Sleep 10ms
> Writing 0x00480A0E @ address 0xFFFFFC2C
> Sleep 10ms
> Writing 0x00000007 @ address 0xFFFFFC30
> Sleep 10ms
> Writing 0x00480100 @ address 0xFFFFFF60
> Sleep 100ms
> JTAG speed set to 12000 kHz
> Downloading 400 bytes @ address 0x00000000
> ERROR: Write memory error @ address 0x00000000, word access: Core error.
> Downloading 828 bytes @ address 0x00000190
> WARNING: Failed to read cacheable memory @ address 0x00000000 Read 4 bytes
@
> address 0x00000000 (Data = 0x00000000)
>
> I think there must be a problem in the linker file but I can't find it.
(it's
> my first time I work with startup and linker files, I just copied the
startup
> file and the linker file and didn't change much)
You don't know what you've done, so you need to start by figuring out what
you have done.
--
Paul Curtis, Rowley Associates Ltd http://www.rowley.co.uk
SolderCore running Defender... http://www.vimeo.com/25709426
> I have a problem with a LPC2468 board. I use Yargato on Eclipse and
configured
> everything as in the description. I changed an example for LPC series to
fit
> the LPC2468. (Amount of flash, ram and adresses)
>
> Compiling is without any errors. When I start the GDB, the segger console
> says:
> Reading all registers
> Read 4 bytes @ address 0x00000000 (Data = 0xE59FF018) Target endianess set
to
> "little endian"
> JTAG speed set to 30 kHz
> ERROR: PC of target system has unexpected value of 0x00000518 after reset.
> Resetting target (SAM7 soft reset)
"SAM7 soft reset" on an LPC2468?
> Sleep 10ms
> Writing 0x00008000 @ address 0xFFFFFD44
> Writing 0x00000601 @ address 0xFFFFFC20
> Sleep 10ms
> Writing 0x00480A0E @ address 0xFFFFFC2C
> Sleep 10ms
> Writing 0x00000007 @ address 0xFFFFFC30
> Sleep 10ms
> Writing 0x00480100 @ address 0xFFFFFF60
> Sleep 100ms
> JTAG speed set to 12000 kHz
> Downloading 400 bytes @ address 0x00000000
> ERROR: Write memory error @ address 0x00000000, word access: Core error.
> Downloading 828 bytes @ address 0x00000190
> WARNING: Failed to read cacheable memory @ address 0x00000000 Read 4 bytes
@
> address 0x00000000 (Data = 0x00000000)
>
> I think there must be a problem in the linker file but I can't find it.
(it's
> my first time I work with startup and linker files, I just copied the
startup
> file and the linker file and didn't change much)
You don't know what you've done, so you need to start by figuring out what
you have done.
--
Paul Curtis, Rowley Associates Ltd http://www.rowley.co.uk
SolderCore running Defender... http://www.vimeo.com/25709426
Reply by ●March 13, 20122012-03-13
I agree, although I don't use a debugger. Some of the addresses shown in
your log don't exist on the LPC2468 (they may for jtag, but i doubt it).
Therefore I think that the problem may be in the debugger config. You could try
and program the LPC2468 through ISP (serial port required). If your program
runs, then it must be a jtag config error.
--- In l..., "Paul Curtis" wrote:
>
> Hi,
>
> > I have a problem with a LPC2468 board. I use Yargato on Eclipse and
> configured
> > everything as in the description. I changed an example for LPC series to
> fit
> > the LPC2468. (Amount of flash, ram and adresses)
> >
> > Compiling is without any errors. When I start the GDB, the segger console
> > says:
> > Reading all registers
> > Read 4 bytes @ address 0x00000000 (Data = 0xE59FF018) Target endianess set
> to
> > "little endian"
> > JTAG speed set to 30 kHz
> > ERROR: PC of target system has unexpected value of 0x00000518 after reset.
> > Resetting target (SAM7 soft reset)
>
> "SAM7 soft reset" on an LPC2468?
>
> > Sleep 10ms
> > Writing 0x00008000 @ address 0xFFFFFD44
> > Writing 0x00000601 @ address 0xFFFFFC20
> > Sleep 10ms
> > Writing 0x00480A0E @ address 0xFFFFFC2C
> > Sleep 10ms
> > Writing 0x00000007 @ address 0xFFFFFC30
> > Sleep 10ms
> > Writing 0x00480100 @ address 0xFFFFFF60
> > Sleep 100ms
> > JTAG speed set to 12000 kHz
> > Downloading 400 bytes @ address 0x00000000
> > ERROR: Write memory error @ address 0x00000000, word access: Core error.
> > Downloading 828 bytes @ address 0x00000190
> > WARNING: Failed to read cacheable memory @ address 0x00000000 Read 4 bytes
> @
> > address 0x00000000 (Data = 0x00000000)
> >
> > I think there must be a problem in the linker file but I can't find it.
> (it's
> > my first time I work with startup and linker files, I just copied the
> startup
> > file and the linker file and didn't change much)
>
> You don't know what you've done, so you need to start by figuring out what
> you have done.
>
> --
> Paul Curtis, Rowley Associates Ltd http://www.rowley.co.uk
> SolderCore running Defender... http://www.vimeo.com/25709426
>
--- In l..., "Paul Curtis" wrote:
>
> Hi,
>
> > I have a problem with a LPC2468 board. I use Yargato on Eclipse and
> configured
> > everything as in the description. I changed an example for LPC series to
> fit
> > the LPC2468. (Amount of flash, ram and adresses)
> >
> > Compiling is without any errors. When I start the GDB, the segger console
> > says:
> > Reading all registers
> > Read 4 bytes @ address 0x00000000 (Data = 0xE59FF018) Target endianess set
> to
> > "little endian"
> > JTAG speed set to 30 kHz
> > ERROR: PC of target system has unexpected value of 0x00000518 after reset.
> > Resetting target (SAM7 soft reset)
>
> "SAM7 soft reset" on an LPC2468?
>
> > Sleep 10ms
> > Writing 0x00008000 @ address 0xFFFFFD44
> > Writing 0x00000601 @ address 0xFFFFFC20
> > Sleep 10ms
> > Writing 0x00480A0E @ address 0xFFFFFC2C
> > Sleep 10ms
> > Writing 0x00000007 @ address 0xFFFFFC30
> > Sleep 10ms
> > Writing 0x00480100 @ address 0xFFFFFF60
> > Sleep 100ms
> > JTAG speed set to 12000 kHz
> > Downloading 400 bytes @ address 0x00000000
> > ERROR: Write memory error @ address 0x00000000, word access: Core error.
> > Downloading 828 bytes @ address 0x00000190
> > WARNING: Failed to read cacheable memory @ address 0x00000000 Read 4 bytes
> @
> > address 0x00000000 (Data = 0x00000000)
> >
> > I think there must be a problem in the linker file but I can't find it.
> (it's
> > my first time I work with startup and linker files, I just copied the
> startup
> > file and the linker file and didn't change much)
>
> You don't know what you've done, so you need to start by figuring out what
> you have done.
>
> --
> Paul Curtis, Rowley Associates Ltd http://www.rowley.co.uk
> SolderCore running Defender... http://www.vimeo.com/25709426
>
Reply by ●March 13, 20122012-03-13
Hi,
how can I program the controller by ISP? A serial port is on the board, that is no problem. But I don't know how to get anything on the controller by ISP, is there any good howto?
My GDB Server does the following:
#
# This config file was tested with J-Link GDB Server v4.10i
#
# Listening for commands on this PC's tcp port 2331
target remote localhost:2331
# Enable flash download and flash breakpoints.
# Flash download and flash breakpoints are features of
# the J-Link software which require separate licenses
# from SEGGER.
# Select flash device
monitor flash device = LPC2468
# Enable FlashDL and FlashBPs
monitor flash download = 1
monitor flash breakpoints = 1
# Set gdb server to little endian
monitor endian little
# Set JTAG speed to adaptive
monitor speed adaptive
# Reset the chip to get to a known state
monitor reset 0
# Setup target,
# remap first 64 bytes to the internal flash
monitor writeu16 0xE01FC040 = 0x0001
monitor writeu16 0xE01FC040
#load
#break main
#continue
My linker file: (should be nearly the same for all arm as i read, just changed the adresses as I found them in the Datasheet.
OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(_start)
MEMORY { /* memory map of LPC2468 */
ROM (rx) : ORIGIN = 0x00000000, LENGTH = 512k
RAM (rwx) : ORIGIN = 0x40000000, LENGTH = 64k
}
/* The sizes of the stacks used by the application. NOTE: you need to adjust */
C_STACK_SIZE = 512;
IRQ_STACK_SIZE = 0;
FIQ_STACK_SIZE = 0;
SVC_STACK_SIZE = 0;
ABT_STACK_SIZE = 0;
UND_STACK_SIZE = 0;
SECTIONS {
.reset : {
*startup.o (.text) /* startup code (ARM vectors and reset handler) */
. = ALIGN(0x4);
} >ROM
.ramvect : { /* used for vectors remapped to RAM */
__ram_start = .;
. = 0x40;
} >RAM
.fastcode : {
__fastcode_load = LOADADDR (.fastcode);
__fastcode_start = .;
*(.glue_7t) *(.glue_7)
*isr.o (.text.*)
*(.text.fastcode)
*(.text.Blinky_dispatch)
/* add other modules here ... */
. = ALIGN (4);
__fastcode_end = .;
} >RAM AT>ROM
.text : {
CREATE_OBJECT_SYMBOLS
*(.text .text.* .gnu.linkonce.t.*)
*(.plt)
*(.gnu.warning)
*(.glue_7t) *(.glue_7) /* NOTE: placed already in .fastcode */
. = ALIGN (4);
/* These are for static constructors and destructors under ELF */
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
*(.rodata .rodata.* .gnu.linkonce.r.*)
*(.ARM.extab* .gnu.linkonce.armextab.*)
*(.gcc_except_table)
*(.eh_frame_hdr)
*(.eh_frame)
*(.init)
*(.fini)
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
PROVIDE_HIDDEN (__fini_array_end = .);
} >ROM
/* .ARM.exidx is sorted, so has to go in its own output section. */
.ARM.exidx : {
__exidx_start = .;
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
__exidx_end = .;
} >ROM
_etext = .;
.data : {
__data_load = LOADADDR (.data);
__data_start = .;
KEEP(*(.jcr))
*(.got.plt) *(.got)
*(.shdata)
*(.data .data.* .gnu.linkonce.d.*)
. = ALIGN (4);
_edata = .;
} >RAM AT>ROM
.bss : {
__bss_start__ = . ;
*(.shbss)
*(.bss .bss.* .gnu.linkonce.b.*)
*(COMMON)
. = ALIGN (8);
__bss_end__ = .;
} >RAM
.stack : {
__stack_start__ = . ;
. += IRQ_STACK_SIZE;
. = ALIGN (4);
__irq_stack_top__ = . ;
. += FIQ_STACK_SIZE;
. = ALIGN (4);
__fiq_stack_top__ = . ;
. += SVC_STACK_SIZE;
. = ALIGN (4);
__svc_stack_top__ = . ;
. += ABT_STACK_SIZE;
. = ALIGN (4);
__abt_stack_top__ = . ;
. += UND_STACK_SIZE;
. = ALIGN (4);
__und_stack_top__ = . ;
. += C_STACK_SIZE;
. = ALIGN (4);
__c_stack_top__ = . ;
__stack_end__ = .;
} >RAM
_end = . ;
__end = . ;
PROVIDE(end = .);
.stab 0 (NOLOAD) : {
*(.stab)
}
.stabstr 0 (NOLOAD) : {
*(.stabstr)
}
/* DWARF debug sections.
* Symbols in the DWARF debugging sections are relative to the beginning
* of the section so we begin them at 0.
*/
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
.note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
.ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }
/DISCARD/ : { *(.note.GNU-stack) }
}
/*** EOF ***/
There are no other configurations and I don't know exactly what all the lines do. And after reading this, I didn't found the adresses that are written at the beginning...
--- In l..., "Kevin" wrote:
>
> I agree, although I don't use a debugger. Some of the addresses shown in your log don't exist on the LPC2468 (they may for jtag, but i doubt it). Therefore I think that the problem may be in the debugger config. You could try and program the LPC2468 through ISP (serial port required). If your program runs, then it must be a jtag config error.
>
> --- In l..., "Paul Curtis" wrote:
> >
> > Hi,
> >
> > > I have a problem with a LPC2468 board. I use Yargato on Eclipse and
> > configured
> > > everything as in the description. I changed an example for LPC series to
> > fit
> > > the LPC2468. (Amount of flash, ram and adresses)
> > >
> > > Compiling is without any errors. When I start the GDB, the segger console
> > > says:
> > > Reading all registers
> > > Read 4 bytes @ address 0x00000000 (Data = 0xE59FF018) Target endianess set
> > to
> > > "little endian"
> > > JTAG speed set to 30 kHz
> > > ERROR: PC of target system has unexpected value of 0x00000518 after reset.
> > > Resetting target (SAM7 soft reset)
> >
> > "SAM7 soft reset" on an LPC2468?
> >
> > > Sleep 10ms
> > > Writing 0x00008000 @ address 0xFFFFFD44
> > > Writing 0x00000601 @ address 0xFFFFFC20
> > > Sleep 10ms
> > > Writing 0x00480A0E @ address 0xFFFFFC2C
> > > Sleep 10ms
> > > Writing 0x00000007 @ address 0xFFFFFC30
> > > Sleep 10ms
> > > Writing 0x00480100 @ address 0xFFFFFF60
> > > Sleep 100ms
> > > JTAG speed set to 12000 kHz
> > > Downloading 400 bytes @ address 0x00000000
> > > ERROR: Write memory error @ address 0x00000000, word access: Core error.
> > > Downloading 828 bytes @ address 0x00000190
> > > WARNING: Failed to read cacheable memory @ address 0x00000000 Read 4 bytes
> > @
> > > address 0x00000000 (Data = 0x00000000)
> > >
> > > I think there must be a problem in the linker file but I can't find it.
> > (it's
> > > my first time I work with startup and linker files, I just copied the
> > startup
> > > file and the linker file and didn't change much)
> >
> > You don't know what you've done, so you need to start by figuring out what
> > you have done.
> >
> > --
> > Paul Curtis, Rowley Associates Ltd http://www.rowley.co.uk
> > SolderCore running Defender... http://www.vimeo.com/25709426
>
how can I program the controller by ISP? A serial port is on the board, that is no problem. But I don't know how to get anything on the controller by ISP, is there any good howto?
My GDB Server does the following:
#
# This config file was tested with J-Link GDB Server v4.10i
#
# Listening for commands on this PC's tcp port 2331
target remote localhost:2331
# Enable flash download and flash breakpoints.
# Flash download and flash breakpoints are features of
# the J-Link software which require separate licenses
# from SEGGER.
# Select flash device
monitor flash device = LPC2468
# Enable FlashDL and FlashBPs
monitor flash download = 1
monitor flash breakpoints = 1
# Set gdb server to little endian
monitor endian little
# Set JTAG speed to adaptive
monitor speed adaptive
# Reset the chip to get to a known state
monitor reset 0
# Setup target,
# remap first 64 bytes to the internal flash
monitor writeu16 0xE01FC040 = 0x0001
monitor writeu16 0xE01FC040
#load
#break main
#continue
My linker file: (should be nearly the same for all arm as i read, just changed the adresses as I found them in the Datasheet.
OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(_start)
MEMORY { /* memory map of LPC2468 */
ROM (rx) : ORIGIN = 0x00000000, LENGTH = 512k
RAM (rwx) : ORIGIN = 0x40000000, LENGTH = 64k
}
/* The sizes of the stacks used by the application. NOTE: you need to adjust */
C_STACK_SIZE = 512;
IRQ_STACK_SIZE = 0;
FIQ_STACK_SIZE = 0;
SVC_STACK_SIZE = 0;
ABT_STACK_SIZE = 0;
UND_STACK_SIZE = 0;
SECTIONS {
.reset : {
*startup.o (.text) /* startup code (ARM vectors and reset handler) */
. = ALIGN(0x4);
} >ROM
.ramvect : { /* used for vectors remapped to RAM */
__ram_start = .;
. = 0x40;
} >RAM
.fastcode : {
__fastcode_load = LOADADDR (.fastcode);
__fastcode_start = .;
*(.glue_7t) *(.glue_7)
*isr.o (.text.*)
*(.text.fastcode)
*(.text.Blinky_dispatch)
/* add other modules here ... */
. = ALIGN (4);
__fastcode_end = .;
} >RAM AT>ROM
.text : {
CREATE_OBJECT_SYMBOLS
*(.text .text.* .gnu.linkonce.t.*)
*(.plt)
*(.gnu.warning)
*(.glue_7t) *(.glue_7) /* NOTE: placed already in .fastcode */
. = ALIGN (4);
/* These are for static constructors and destructors under ELF */
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
*(.rodata .rodata.* .gnu.linkonce.r.*)
*(.ARM.extab* .gnu.linkonce.armextab.*)
*(.gcc_except_table)
*(.eh_frame_hdr)
*(.eh_frame)
*(.init)
*(.fini)
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
PROVIDE_HIDDEN (__fini_array_end = .);
} >ROM
/* .ARM.exidx is sorted, so has to go in its own output section. */
.ARM.exidx : {
__exidx_start = .;
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
__exidx_end = .;
} >ROM
_etext = .;
.data : {
__data_load = LOADADDR (.data);
__data_start = .;
KEEP(*(.jcr))
*(.got.plt) *(.got)
*(.shdata)
*(.data .data.* .gnu.linkonce.d.*)
. = ALIGN (4);
_edata = .;
} >RAM AT>ROM
.bss : {
__bss_start__ = . ;
*(.shbss)
*(.bss .bss.* .gnu.linkonce.b.*)
*(COMMON)
. = ALIGN (8);
__bss_end__ = .;
} >RAM
.stack : {
__stack_start__ = . ;
. += IRQ_STACK_SIZE;
. = ALIGN (4);
__irq_stack_top__ = . ;
. += FIQ_STACK_SIZE;
. = ALIGN (4);
__fiq_stack_top__ = . ;
. += SVC_STACK_SIZE;
. = ALIGN (4);
__svc_stack_top__ = . ;
. += ABT_STACK_SIZE;
. = ALIGN (4);
__abt_stack_top__ = . ;
. += UND_STACK_SIZE;
. = ALIGN (4);
__und_stack_top__ = . ;
. += C_STACK_SIZE;
. = ALIGN (4);
__c_stack_top__ = . ;
__stack_end__ = .;
} >RAM
_end = . ;
__end = . ;
PROVIDE(end = .);
.stab 0 (NOLOAD) : {
*(.stab)
}
.stabstr 0 (NOLOAD) : {
*(.stabstr)
}
/* DWARF debug sections.
* Symbols in the DWARF debugging sections are relative to the beginning
* of the section so we begin them at 0.
*/
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
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.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
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.note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
.ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }
/DISCARD/ : { *(.note.GNU-stack) }
}
/*** EOF ***/
There are no other configurations and I don't know exactly what all the lines do. And after reading this, I didn't found the adresses that are written at the beginning...
--- In l..., "Kevin" wrote:
>
> I agree, although I don't use a debugger. Some of the addresses shown in your log don't exist on the LPC2468 (they may for jtag, but i doubt it). Therefore I think that the problem may be in the debugger config. You could try and program the LPC2468 through ISP (serial port required). If your program runs, then it must be a jtag config error.
>
> --- In l..., "Paul Curtis" wrote:
> >
> > Hi,
> >
> > > I have a problem with a LPC2468 board. I use Yargato on Eclipse and
> > configured
> > > everything as in the description. I changed an example for LPC series to
> > fit
> > > the LPC2468. (Amount of flash, ram and adresses)
> > >
> > > Compiling is without any errors. When I start the GDB, the segger console
> > > says:
> > > Reading all registers
> > > Read 4 bytes @ address 0x00000000 (Data = 0xE59FF018) Target endianess set
> > to
> > > "little endian"
> > > JTAG speed set to 30 kHz
> > > ERROR: PC of target system has unexpected value of 0x00000518 after reset.
> > > Resetting target (SAM7 soft reset)
> >
> > "SAM7 soft reset" on an LPC2468?
> >
> > > Sleep 10ms
> > > Writing 0x00008000 @ address 0xFFFFFD44
> > > Writing 0x00000601 @ address 0xFFFFFC20
> > > Sleep 10ms
> > > Writing 0x00480A0E @ address 0xFFFFFC2C
> > > Sleep 10ms
> > > Writing 0x00000007 @ address 0xFFFFFC30
> > > Sleep 10ms
> > > Writing 0x00480100 @ address 0xFFFFFF60
> > > Sleep 100ms
> > > JTAG speed set to 12000 kHz
> > > Downloading 400 bytes @ address 0x00000000
> > > ERROR: Write memory error @ address 0x00000000, word access: Core error.
> > > Downloading 828 bytes @ address 0x00000190
> > > WARNING: Failed to read cacheable memory @ address 0x00000000 Read 4 bytes
> > @
> > > address 0x00000000 (Data = 0x00000000)
> > >
> > > I think there must be a problem in the linker file but I can't find it.
> > (it's
> > > my first time I work with startup and linker files, I just copied the
> > startup
> > > file and the linker file and didn't change much)
> >
> > You don't know what you've done, so you need to start by figuring out what
> > you have done.
> >
> > --
> > Paul Curtis, Rowley Associates Ltd http://www.rowley.co.uk
> > SolderCore running Defender... http://www.vimeo.com/25709426
>
Reply by ●March 13, 20122012-03-13
For ISP use "Flash Magic" a free tool made by "Embedded Systems Academy"
--- In l..., "lemartes86" wrote:
>
> Hi,
> how can I program the controller by ISP? A serial port is on the board, that is no problem. But I don't know how to get anything on the controller by ISP, is there any good howto?
>
> My GDB Server does the following:
> #
> # This config file was tested with J-Link GDB Server v4.10i
> #
>
> # Listening for commands on this PC's tcp port 2331
> target remote localhost:2331
>
> # Enable flash download and flash breakpoints.
> # Flash download and flash breakpoints are features of
> # the J-Link software which require separate licenses
> # from SEGGER.
>
> # Select flash device
> monitor flash device = LPC2468
>
> # Enable FlashDL and FlashBPs
> monitor flash download = 1
> monitor flash breakpoints = 1
>
> # Set gdb server to little endian
> monitor endian little
>
> # Set JTAG speed to adaptive
> monitor speed adaptive
>
> # Reset the chip to get to a known state
> monitor reset 0
>
> # Setup target,
> # remap first 64 bytes to the internal flash
> monitor writeu16 0xE01FC040 = 0x0001
> monitor writeu16 0xE01FC040
>
> #load
> #break main
> #continue
>
>
> My linker file: (should be nearly the same for all arm as i read, just changed the adresses as I found them in the Datasheet.
> OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
> OUTPUT_ARCH(arm)
> ENTRY(_start)
>
> MEMORY { /* memory map of LPC2468 */
> ROM (rx) : ORIGIN = 0x00000000, LENGTH = 512k
> RAM (rwx) : ORIGIN = 0x40000000, LENGTH = 64k
> }
>
> /* The sizes of the stacks used by the application. NOTE: you need to adjust */
> C_STACK_SIZE = 512;
> IRQ_STACK_SIZE = 0;
> FIQ_STACK_SIZE = 0;
> SVC_STACK_SIZE = 0;
> ABT_STACK_SIZE = 0;
> UND_STACK_SIZE = 0;
>
>
> SECTIONS {
>
> .reset : {
> *startup.o (.text) /* startup code (ARM vectors and reset handler) */
> . = ALIGN(0x4);
> } >ROM
>
> .ramvect : { /* used for vectors remapped to RAM */
> __ram_start = .;
> . = 0x40;
> } >RAM
>
> .fastcode : {
> __fastcode_load = LOADADDR (.fastcode);
> __fastcode_start = .;
>
> *(.glue_7t) *(.glue_7)
> *isr.o (.text.*)
> *(.text.fastcode)
> *(.text.Blinky_dispatch)
> /* add other modules here ... */
>
> . = ALIGN (4);
> __fastcode_end = .;
> } >RAM AT>ROM
>
> .text : {
> CREATE_OBJECT_SYMBOLS
> *(.text .text.* .gnu.linkonce.t.*)
> *(.plt)
> *(.gnu.warning)
> *(.glue_7t) *(.glue_7) /* NOTE: placed already in .fastcode */
>
> . = ALIGN (4);
> /* These are for static constructors and destructors under ELF */
> KEEP (*crtbegin.o(.ctors))
> KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
> KEEP (*(SORT(.ctors.*)))
> KEEP (*crtend.o(.ctors))
> KEEP (*crtbegin.o(.dtors))
> KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
> KEEP (*(SORT(.dtors.*)))
> KEEP (*crtend.o(.dtors))
>
> *(.rodata .rodata.* .gnu.linkonce.r.*)
>
> *(.ARM.extab* .gnu.linkonce.armextab.*)
> *(.gcc_except_table)
> *(.eh_frame_hdr)
> *(.eh_frame)
>
> *(.init)
> *(.fini)
>
> PROVIDE_HIDDEN (__preinit_array_start = .);
> KEEP (*(.preinit_array))
> PROVIDE_HIDDEN (__preinit_array_end = .);
> PROVIDE_HIDDEN (__init_array_start = .);
> KEEP (*(SORT(.init_array.*)))
> KEEP (*(.init_array))
> PROVIDE_HIDDEN (__init_array_end = .);
> PROVIDE_HIDDEN (__fini_array_start = .);
> KEEP (*(.fini_array))
> KEEP (*(SORT(.fini_array.*)))
> PROVIDE_HIDDEN (__fini_array_end = .);
> } >ROM
>
> /* .ARM.exidx is sorted, so has to go in its own output section. */
> .ARM.exidx : {
> __exidx_start = .;
> *(.ARM.exidx* .gnu.linkonce.armexidx.*)
> __exidx_end = .;
> } >ROM
> _etext = .;
>
> .data : {
> __data_load = LOADADDR (.data);
> __data_start = .;
> KEEP(*(.jcr))
> *(.got.plt) *(.got)
> *(.shdata)
> *(.data .data.* .gnu.linkonce.d.*)
> . = ALIGN (4);
> _edata = .;
> } >RAM AT>ROM
>
> .bss : {
> __bss_start__ = . ;
> *(.shbss)
> *(.bss .bss.* .gnu.linkonce.b.*)
> *(COMMON)
> . = ALIGN (8);
> __bss_end__ = .;
> } >RAM
>
> .stack : {
> __stack_start__ = . ;
>
> . += IRQ_STACK_SIZE;
> . = ALIGN (4);
> __irq_stack_top__ = . ;
>
> . += FIQ_STACK_SIZE;
> . = ALIGN (4);
> __fiq_stack_top__ = . ;
>
> . += SVC_STACK_SIZE;
> . = ALIGN (4);
> __svc_stack_top__ = . ;
>
> . += ABT_STACK_SIZE;
> . = ALIGN (4);
> __abt_stack_top__ = . ;
>
> . += UND_STACK_SIZE;
> . = ALIGN (4);
> __und_stack_top__ = . ;
>
> . += C_STACK_SIZE;
> . = ALIGN (4);
> __c_stack_top__ = . ;
>
> __stack_end__ = .;
> } >RAM
>
> _end = . ;
> __end = . ;
> PROVIDE(end = .);
>
> .stab 0 (NOLOAD) : {
> *(.stab)
> }
>
> .stabstr 0 (NOLOAD) : {
> *(.stabstr)
> }
>
> /* DWARF debug sections.
> * Symbols in the DWARF debugging sections are relative to the beginning
> * of the section so we begin them at 0.
> */
> /* DWARF 1 */
> .debug 0 : { *(.debug) }
> .line 0 : { *(.line) }
> /* GNU DWARF 1 extensions */
> .debug_srcinfo 0 : { *(.debug_srcinfo) }
> .debug_sfnames 0 : { *(.debug_sfnames) }
> /* DWARF 1.1 and DWARF 2 */
> .debug_aranges 0 : { *(.debug_aranges) }
> .debug_pubnames 0 : { *(.debug_pubnames) }
> /* DWARF 2 */
> .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
> .debug_abbrev 0 : { *(.debug_abbrev) }
> .debug_line 0 : { *(.debug_line) }
> .debug_frame 0 : { *(.debug_frame) }
> .debug_str 0 : { *(.debug_str) }
> .debug_loc 0 : { *(.debug_loc) }
> .debug_macinfo 0 : { *(.debug_macinfo) }
> /* SGI/MIPS DWARF 2 extensions */
> .debug_weaknames 0 : { *(.debug_weaknames) }
> .debug_funcnames 0 : { *(.debug_funcnames) }
> .debug_typenames 0 : { *(.debug_typenames) }
> .debug_varnames 0 : { *(.debug_varnames) }
> .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
> .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }
> /DISCARD/ : { *(.note.GNU-stack) }
> }
>
> /*** EOF ***/
>
> There are no other configurations and I don't know exactly what all the lines do. And after reading this, I didn't found the adresses that are written at the beginning...
>
>
> --- In l..., "Kevin" wrote:
> >
> > I agree, although I don't use a debugger. Some of the addresses shown in your log don't exist on the LPC2468 (they may for jtag, but i doubt it). Therefore I think that the problem may be in the debugger config. You could try and program the LPC2468 through ISP (serial port required). If your program runs, then it must be a jtag config error.
> >
> > --- In l..., "Paul Curtis" wrote:
> > >
> > > Hi,
> > >
> > > > I have a problem with a LPC2468 board. I use Yargato on Eclipse and
> > > configured
> > > > everything as in the description. I changed an example for LPC series to
> > > fit
> > > > the LPC2468. (Amount of flash, ram and adresses)
> > > >
> > > > Compiling is without any errors. When I start the GDB, the segger console
> > > > says:
> > > > Reading all registers
> > > > Read 4 bytes @ address 0x00000000 (Data = 0xE59FF018) Target endianess set
> > > to
> > > > "little endian"
> > > > JTAG speed set to 30 kHz
> > > > ERROR: PC of target system has unexpected value of 0x00000518 after reset.
> > > > Resetting target (SAM7 soft reset)
> > >
> > > "SAM7 soft reset" on an LPC2468?
> > >
> > > > Sleep 10ms
> > > > Writing 0x00008000 @ address 0xFFFFFD44
> > > > Writing 0x00000601 @ address 0xFFFFFC20
> > > > Sleep 10ms
> > > > Writing 0x00480A0E @ address 0xFFFFFC2C
> > > > Sleep 10ms
> > > > Writing 0x00000007 @ address 0xFFFFFC30
> > > > Sleep 10ms
> > > > Writing 0x00480100 @ address 0xFFFFFF60
> > > > Sleep 100ms
> > > > JTAG speed set to 12000 kHz
> > > > Downloading 400 bytes @ address 0x00000000
> > > > ERROR: Write memory error @ address 0x00000000, word access: Core error.
> > > > Downloading 828 bytes @ address 0x00000190
> > > > WARNING: Failed to read cacheable memory @ address 0x00000000 Read 4 bytes
> > > @
> > > > address 0x00000000 (Data = 0x00000000)
> > > >
> > > > I think there must be a problem in the linker file but I can't find it.
> > > (it's
> > > > my first time I work with startup and linker files, I just copied the
> > > startup
> > > > file and the linker file and didn't change much)
> > >
> > > You don't know what you've done, so you need to start by figuring out what
> > > you have done.
> > >
> > > --
> > > Paul Curtis, Rowley Associates Ltd http://www.rowley.co.uk
> > > SolderCore running Defender... http://www.vimeo.com/25709426
> > >
>
--- In l..., "lemartes86" wrote:
>
> Hi,
> how can I program the controller by ISP? A serial port is on the board, that is no problem. But I don't know how to get anything on the controller by ISP, is there any good howto?
>
> My GDB Server does the following:
> #
> # This config file was tested with J-Link GDB Server v4.10i
> #
>
> # Listening for commands on this PC's tcp port 2331
> target remote localhost:2331
>
> # Enable flash download and flash breakpoints.
> # Flash download and flash breakpoints are features of
> # the J-Link software which require separate licenses
> # from SEGGER.
>
> # Select flash device
> monitor flash device = LPC2468
>
> # Enable FlashDL and FlashBPs
> monitor flash download = 1
> monitor flash breakpoints = 1
>
> # Set gdb server to little endian
> monitor endian little
>
> # Set JTAG speed to adaptive
> monitor speed adaptive
>
> # Reset the chip to get to a known state
> monitor reset 0
>
> # Setup target,
> # remap first 64 bytes to the internal flash
> monitor writeu16 0xE01FC040 = 0x0001
> monitor writeu16 0xE01FC040
>
> #load
> #break main
> #continue
>
>
> My linker file: (should be nearly the same for all arm as i read, just changed the adresses as I found them in the Datasheet.
> OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
> OUTPUT_ARCH(arm)
> ENTRY(_start)
>
> MEMORY { /* memory map of LPC2468 */
> ROM (rx) : ORIGIN = 0x00000000, LENGTH = 512k
> RAM (rwx) : ORIGIN = 0x40000000, LENGTH = 64k
> }
>
> /* The sizes of the stacks used by the application. NOTE: you need to adjust */
> C_STACK_SIZE = 512;
> IRQ_STACK_SIZE = 0;
> FIQ_STACK_SIZE = 0;
> SVC_STACK_SIZE = 0;
> ABT_STACK_SIZE = 0;
> UND_STACK_SIZE = 0;
>
>
> SECTIONS {
>
> .reset : {
> *startup.o (.text) /* startup code (ARM vectors and reset handler) */
> . = ALIGN(0x4);
> } >ROM
>
> .ramvect : { /* used for vectors remapped to RAM */
> __ram_start = .;
> . = 0x40;
> } >RAM
>
> .fastcode : {
> __fastcode_load = LOADADDR (.fastcode);
> __fastcode_start = .;
>
> *(.glue_7t) *(.glue_7)
> *isr.o (.text.*)
> *(.text.fastcode)
> *(.text.Blinky_dispatch)
> /* add other modules here ... */
>
> . = ALIGN (4);
> __fastcode_end = .;
> } >RAM AT>ROM
>
> .text : {
> CREATE_OBJECT_SYMBOLS
> *(.text .text.* .gnu.linkonce.t.*)
> *(.plt)
> *(.gnu.warning)
> *(.glue_7t) *(.glue_7) /* NOTE: placed already in .fastcode */
>
> . = ALIGN (4);
> /* These are for static constructors and destructors under ELF */
> KEEP (*crtbegin.o(.ctors))
> KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
> KEEP (*(SORT(.ctors.*)))
> KEEP (*crtend.o(.ctors))
> KEEP (*crtbegin.o(.dtors))
> KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
> KEEP (*(SORT(.dtors.*)))
> KEEP (*crtend.o(.dtors))
>
> *(.rodata .rodata.* .gnu.linkonce.r.*)
>
> *(.ARM.extab* .gnu.linkonce.armextab.*)
> *(.gcc_except_table)
> *(.eh_frame_hdr)
> *(.eh_frame)
>
> *(.init)
> *(.fini)
>
> PROVIDE_HIDDEN (__preinit_array_start = .);
> KEEP (*(.preinit_array))
> PROVIDE_HIDDEN (__preinit_array_end = .);
> PROVIDE_HIDDEN (__init_array_start = .);
> KEEP (*(SORT(.init_array.*)))
> KEEP (*(.init_array))
> PROVIDE_HIDDEN (__init_array_end = .);
> PROVIDE_HIDDEN (__fini_array_start = .);
> KEEP (*(.fini_array))
> KEEP (*(SORT(.fini_array.*)))
> PROVIDE_HIDDEN (__fini_array_end = .);
> } >ROM
>
> /* .ARM.exidx is sorted, so has to go in its own output section. */
> .ARM.exidx : {
> __exidx_start = .;
> *(.ARM.exidx* .gnu.linkonce.armexidx.*)
> __exidx_end = .;
> } >ROM
> _etext = .;
>
> .data : {
> __data_load = LOADADDR (.data);
> __data_start = .;
> KEEP(*(.jcr))
> *(.got.plt) *(.got)
> *(.shdata)
> *(.data .data.* .gnu.linkonce.d.*)
> . = ALIGN (4);
> _edata = .;
> } >RAM AT>ROM
>
> .bss : {
> __bss_start__ = . ;
> *(.shbss)
> *(.bss .bss.* .gnu.linkonce.b.*)
> *(COMMON)
> . = ALIGN (8);
> __bss_end__ = .;
> } >RAM
>
> .stack : {
> __stack_start__ = . ;
>
> . += IRQ_STACK_SIZE;
> . = ALIGN (4);
> __irq_stack_top__ = . ;
>
> . += FIQ_STACK_SIZE;
> . = ALIGN (4);
> __fiq_stack_top__ = . ;
>
> . += SVC_STACK_SIZE;
> . = ALIGN (4);
> __svc_stack_top__ = . ;
>
> . += ABT_STACK_SIZE;
> . = ALIGN (4);
> __abt_stack_top__ = . ;
>
> . += UND_STACK_SIZE;
> . = ALIGN (4);
> __und_stack_top__ = . ;
>
> . += C_STACK_SIZE;
> . = ALIGN (4);
> __c_stack_top__ = . ;
>
> __stack_end__ = .;
> } >RAM
>
> _end = . ;
> __end = . ;
> PROVIDE(end = .);
>
> .stab 0 (NOLOAD) : {
> *(.stab)
> }
>
> .stabstr 0 (NOLOAD) : {
> *(.stabstr)
> }
>
> /* DWARF debug sections.
> * Symbols in the DWARF debugging sections are relative to the beginning
> * of the section so we begin them at 0.
> */
> /* DWARF 1 */
> .debug 0 : { *(.debug) }
> .line 0 : { *(.line) }
> /* GNU DWARF 1 extensions */
> .debug_srcinfo 0 : { *(.debug_srcinfo) }
> .debug_sfnames 0 : { *(.debug_sfnames) }
> /* DWARF 1.1 and DWARF 2 */
> .debug_aranges 0 : { *(.debug_aranges) }
> .debug_pubnames 0 : { *(.debug_pubnames) }
> /* DWARF 2 */
> .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
> .debug_abbrev 0 : { *(.debug_abbrev) }
> .debug_line 0 : { *(.debug_line) }
> .debug_frame 0 : { *(.debug_frame) }
> .debug_str 0 : { *(.debug_str) }
> .debug_loc 0 : { *(.debug_loc) }
> .debug_macinfo 0 : { *(.debug_macinfo) }
> /* SGI/MIPS DWARF 2 extensions */
> .debug_weaknames 0 : { *(.debug_weaknames) }
> .debug_funcnames 0 : { *(.debug_funcnames) }
> .debug_typenames 0 : { *(.debug_typenames) }
> .debug_varnames 0 : { *(.debug_varnames) }
> .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
> .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }
> /DISCARD/ : { *(.note.GNU-stack) }
> }
>
> /*** EOF ***/
>
> There are no other configurations and I don't know exactly what all the lines do. And after reading this, I didn't found the adresses that are written at the beginning...
>
>
> --- In l..., "Kevin" wrote:
> >
> > I agree, although I don't use a debugger. Some of the addresses shown in your log don't exist on the LPC2468 (they may for jtag, but i doubt it). Therefore I think that the problem may be in the debugger config. You could try and program the LPC2468 through ISP (serial port required). If your program runs, then it must be a jtag config error.
> >
> > --- In l..., "Paul Curtis" wrote:
> > >
> > > Hi,
> > >
> > > > I have a problem with a LPC2468 board. I use Yargato on Eclipse and
> > > configured
> > > > everything as in the description. I changed an example for LPC series to
> > > fit
> > > > the LPC2468. (Amount of flash, ram and adresses)
> > > >
> > > > Compiling is without any errors. When I start the GDB, the segger console
> > > > says:
> > > > Reading all registers
> > > > Read 4 bytes @ address 0x00000000 (Data = 0xE59FF018) Target endianess set
> > > to
> > > > "little endian"
> > > > JTAG speed set to 30 kHz
> > > > ERROR: PC of target system has unexpected value of 0x00000518 after reset.
> > > > Resetting target (SAM7 soft reset)
> > >
> > > "SAM7 soft reset" on an LPC2468?
> > >
> > > > Sleep 10ms
> > > > Writing 0x00008000 @ address 0xFFFFFD44
> > > > Writing 0x00000601 @ address 0xFFFFFC20
> > > > Sleep 10ms
> > > > Writing 0x00480A0E @ address 0xFFFFFC2C
> > > > Sleep 10ms
> > > > Writing 0x00000007 @ address 0xFFFFFC30
> > > > Sleep 10ms
> > > > Writing 0x00480100 @ address 0xFFFFFF60
> > > > Sleep 100ms
> > > > JTAG speed set to 12000 kHz
> > > > Downloading 400 bytes @ address 0x00000000
> > > > ERROR: Write memory error @ address 0x00000000, word access: Core error.
> > > > Downloading 828 bytes @ address 0x00000190
> > > > WARNING: Failed to read cacheable memory @ address 0x00000000 Read 4 bytes
> > > @
> > > > address 0x00000000 (Data = 0x00000000)
> > > >
> > > > I think there must be a problem in the linker file but I can't find it.
> > > (it's
> > > > my first time I work with startup and linker files, I just copied the
> > > startup
> > > > file and the linker file and didn't change much)
> > >
> > > You don't know what you've done, so you need to start by figuring out what
> > > you have done.
> > >
> > > --
> > > Paul Curtis, Rowley Associates Ltd http://www.rowley.co.uk
> > > SolderCore running Defender... http://www.vimeo.com/25709426
> > >
>
Reply by ●March 13, 20122012-03-13
Il 13/03/2012 11:11, lemartes86 ha scritto:
>
>
> I have a problem with a LPC2468 board. I use Yargato on Eclipse and
> configured everything as in the description. I changed an example for
> LPC series to fit the LPC2468. (Amount of flash, ram and adresses)
>
J-Link is able to recognize the core but if you are using GDB server it
depends by .gdbinit file (that it is called .jlink or .gdb by Segger).
You have to edit it to adapt to your hw.
This is an example from Jlink-lite installation (folder GDBInit)
for an LPC2378 so I think it may work with LPC2478 also:
# Connect to the J-Link gdb server
target remote localhost:2331
# Select flash device
monitor flash device = LPC2378
# Set gdb server to little endian
monitor endian little
# Set speed to JTAG speed adaptive
monitor speed adaptive
# Reset the target
monitor reset 0
# Map at the first 64 bytes the internal flash
monitor long 0xE01FC040 = 0x00000001
break main
# Load the ELF-file
load
# Let the application run to main()
continue
> Compiling is without any errors. When I start the GDB, the segger
> console says:
> Reading all registers
> Read 4 bytes @ address 0x00000000 (Data = 0xE59FF018)
> Target endianess set to "little endian"
> JTAG speed set to 30 kHz
> ERROR: PC of target system has unexpected value of 0x00000518 after reset.
> Resetting target (SAM7 soft reset)
> Sleep 10ms
> Writing 0x00008000 @ address 0xFFFFFD44
> Writing 0x00000601 @ address 0xFFFFFC20
> Sleep 10ms
> Writing 0x00480A0E @ address 0xFFFFFC2C
> Sleep 10ms
> Writing 0x00000007 @ address 0xFFFFFC30
> Sleep 10ms
> Writing 0x00480100 @ address 0xFFFFFF60
> Sleep 100ms
> JTAG speed set to 12000 kHz
> Downloading 400 bytes @ address 0x00000000
> ERROR: Write memory error @ address 0x00000000, word access: Core error.
> Downloading 828 bytes @ address 0x00000190
> WARNING: Failed to read cacheable memory @ address 0x00000000
> Read 4 bytes @ address 0x00000000 (Data = 0x00000000)
>
> I think there must be a problem in the linker file but I can't find
> it. (it's my first time I work with startup and linker files, I just
> copied the startup file and the linker file and didn't change much)
>
> Maybe somebody has such files that are definetly running on this
> processor or cann help me with it.
>
>
> I have a problem with a LPC2468 board. I use Yargato on Eclipse and
> configured everything as in the description. I changed an example for
> LPC series to fit the LPC2468. (Amount of flash, ram and adresses)
>
J-Link is able to recognize the core but if you are using GDB server it
depends by .gdbinit file (that it is called .jlink or .gdb by Segger).
You have to edit it to adapt to your hw.
This is an example from Jlink-lite installation (folder GDBInit)
for an LPC2378 so I think it may work with LPC2478 also:
# Connect to the J-Link gdb server
target remote localhost:2331
# Select flash device
monitor flash device = LPC2378
# Set gdb server to little endian
monitor endian little
# Set speed to JTAG speed adaptive
monitor speed adaptive
# Reset the target
monitor reset 0
# Map at the first 64 bytes the internal flash
monitor long 0xE01FC040 = 0x00000001
break main
# Load the ELF-file
load
# Let the application run to main()
continue
> Compiling is without any errors. When I start the GDB, the segger
> console says:
> Reading all registers
> Read 4 bytes @ address 0x00000000 (Data = 0xE59FF018)
> Target endianess set to "little endian"
> JTAG speed set to 30 kHz
> ERROR: PC of target system has unexpected value of 0x00000518 after reset.
> Resetting target (SAM7 soft reset)
> Sleep 10ms
> Writing 0x00008000 @ address 0xFFFFFD44
> Writing 0x00000601 @ address 0xFFFFFC20
> Sleep 10ms
> Writing 0x00480A0E @ address 0xFFFFFC2C
> Sleep 10ms
> Writing 0x00000007 @ address 0xFFFFFC30
> Sleep 10ms
> Writing 0x00480100 @ address 0xFFFFFF60
> Sleep 100ms
> JTAG speed set to 12000 kHz
> Downloading 400 bytes @ address 0x00000000
> ERROR: Write memory error @ address 0x00000000, word access: Core error.
> Downloading 828 bytes @ address 0x00000190
> WARNING: Failed to read cacheable memory @ address 0x00000000
> Read 4 bytes @ address 0x00000000 (Data = 0x00000000)
>
> I think there must be a problem in the linker file but I can't find
> it. (it's my first time I work with startup and linker files, I just
> copied the startup file and the linker file and didn't change much)
>
> Maybe somebody has such files that are definetly running on this
> processor or cann help me with it.
