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Working With CMSIS libray in IAR

Started by Mohammad August 25, 2012
Hi

I didn't anything about CMSIS until know and I started to work with them. I have seen a movie from "Matt Saunders: Working with CMSIS-RTOS" that describes how we can use these libraries. Some questions stuck in my mind.
In the movie shows there is a configuration wizard window in the keil IDE, we can define our project and set clock and other things through that. Is any similar window our option for IAR IDE (Or always I should define options by changing the code)?
In the template example of CMSIS we have two workspace the first one is called "LPC1700CMSIS-Flash" and the other one is "LPC1700CMSIS-Ram" (I know we use two workspace to separate the release options from debug mode) but why they called Flash and ram, is anything special that I don't know?
I'd appreciate any useful resources you can give me in order to help me get information.

Thanks a lot
Yousefi

An Engineer's Guide to the LPC2100 Series

On Sun, Aug 26, 2012 at 1:58 AM, Mohammad wrote:
> In the template example of CMSIS we have two workspace the first one is called "LPC1700CMSIS-Flash" and the other one is "LPC1700CMSIS-Ram" (I know we use two workspace to separate the release options from debug mode) but why they called Flash and ram, is anything special that I don't know?

LPC17xx is a von-neumann architecture chip. This means that it has one
memory space into which both flash and ram are mapped. As a result,
code can be run directly from flash, or loaded into ram and run from
there.
The addresses in your linked binary will be different depending on the
location that the code runs from.
The two profiles allow you to specify which memory your code will run
from, so the linker can use appropriate addresses.
Thanks for your reply Triffid, However in the datasheet says: "The ARM Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals" but the linker's has different linker configuration file as you told me.

--- In l..., Triffid Hunter
> LPC17xx is a von-neumann architecture chip. This means that it has one
> memory space into which both flash and ram are mapped. As a result,
> code can be run directly from flash, or loaded into ram and run from
> there.

Il 26/08/2012 11:47, Triffid Hunter ha scritto:
>
>
> On Sun, Aug 26, 2012 at 1:58 AM, Mohammad > > wrote:
> > In the template example of CMSIS we have two workspace the first one
> is called "LPC1700CMSIS-Flash" and the other one is "LPC1700CMSIS-Ram"
> (I know we use two workspace to separate the release options from
> debug mode) but why they called Flash and ram, is anything special
> that I don't know?
>
> LPC17xx is a von-neumann architecture chip.
>
This is not true, it is an Harvard architecture type with 3 stage
pipeline and multiple buses, also different memories have separate
buses, this permits to have multiple DMA channels operating without any
interference with the cpu. The memory space is then divided using a
memory scheme that resembles that of a Von Neumann cpu but this because
permits the same efficiency for the C compilers permitting to
distinguish the right memory access by the memory address. This simplify
the C source code compared with other Harvard architectures as Atmel AVR
and Microchip PICs. ARM7 are Von Neumann cpu, ARM9 are Harvard cpu and
Cortex-M3 and M4 are Harvard enhanced cpu and finally Cortex-M0 are Von
Neumann cpu using an AHB-Lite bus system so it is a little bit different
then a traditional Von Neumann cpu.
>
> This means that it has one
> memory space into which both flash and ram are mapped. As a result,
> code can be run directly from flash, or loaded into ram and run from
> there.
>
See previous note, the situation is a little bit different but it is
possible to execute the code from every memory space.
>
> The addresses in your linked binary will be different depending on the
> location that the code runs from.
> The two profiles allow you to specify which memory your code will run
> from, so the linker can use appropriate addresses.
>
This is correct.



Il 26/08/2012 15:09, Mohammad ha scritto:
>
>
> Thanks for your reply Triffid, However in the datasheet says: "The ARM
> Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard
> architecture with separate local instruction and data buses as well as
> a third bus for peripherals" but the linker's has different linker
> configuration file as you told me.
>
Yes, correct it is an Harvard but it uses AHB bus (AMBA High performance
Bus) so it is the bus that makes possible to execute the code also from
memory that should be devoted only to data space.
So ARM cores are more then a CPU core are a complex architecture made of
several simple bricks that all together made probably the best
microcontroller architecture seen in the world until now.
> --- In l... ,
> Triffid Hunter
> > LPC17xx is a von-neumann architecture chip. This means that it has one
> > memory space into which both flash and ram are mapped. As a result,
> > code can be run directly from flash, or loaded into ram and run from
> > there.



Thanks for your lucid explanation.
I just started to work with ARM processor. would you please give me some resources or links for using CMSIS?

--- In l..., "M. Manca" wrote:
>
> Il 26/08/2012 15:09, Mohammad ha scritto:
> >
> >
> > Thanks for your reply Triffid, However in the datasheet says: "The ARM
> > Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard
> > architecture with separate local instruction and data buses as well as
> > a third bus for peripherals" but the linker's has different linker
> > configuration file as you told me.
> >
> Yes, correct it is an Harvard but it uses AHB bus (AMBA High performance
> Bus) so it is the bus that makes possible to execute the code also from
> memory that should be devoted only to data space.
> So ARM cores are more then a CPU core are a complex architecture made of
> several simple bricks that all together made probably the best
> microcontroller architecture seen in the world until now.
> >
> >
> > --- In l... ,
> > Triffid Hunter
> > > LPC17xx is a von-neumann architecture chip. This means that it has one
> > > memory space into which both flash and ram are mapped. As a result,
> > > code can be run directly from flash, or loaded into ram and run from
> > > there.
> >
> >
>

Salaam Yousefi,

If you're looking for an alternative to the Keil Configuration Wizard, have
a look at my own CMSIS Configuration Wizard, which you can find at
helmpcb.com/software/cmsis-configuration-wizard.

Amr


Il 26/08/2012 22:21, Mohammad ha scritto:
>
>
> Thanks for your lucid explanation.
> I just started to work with ARM processor. would you please give me
> some resources or links for using CMSIS?
>
CMSIS is a standard established by ARM with the intent of standardize a
minimum library (this written by ARM) to simplify the startup of the
Cortex based microcontrollers and the standard peripherals part of the
minimum set delivered with Cortex cores. So, to find and read the
general documentation about CMSIS you should register on the ARM web
site. Also at
http://www.keil.com/support/man/docs/gsac/gsac_cmsisoverview.htm you can
find useful informations but best of all you could visit www.onarm.com

But take care that ARM "imposes" silicon vendors to realize a library
following CMSIS guidelines to be CMSIS compliant, so it should be a 2
learning steps, one for the general ARM CMSIS implementation and the
other for the silicon vendor implementation.

Of course if you need just to use a CMSIS implementation you should use
that delivered by the silicon vendor and take care that you may find
some little differences also between 2 CMSIS implementations related to
2 different microcontrollers also if they are made by the same silicon
vendor.
> --- In l... , "M.
> Manca" wrote:
> >
> > Il 26/08/2012 15:09, Mohammad ha scritto:
> > >
> > >
> > > Thanks for your reply Triffid, However in the datasheet says: "The ARM
> > > Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard
> > > architecture with separate local instruction and data buses as well as
> > > a third bus for peripherals" but the linker's has different linker
> > > configuration file as you told me.
> > >
> > Yes, correct it is an Harvard but it uses AHB bus (AMBA High performance
> > Bus) so it is the bus that makes possible to execute the code also from
> > memory that should be devoted only to data space.
> > So ARM cores are more then a CPU core are a complex architecture made of
> > several simple bricks that all together made probably the best
> > microcontroller architecture seen in the world until now.
> > >
> > >
> > > --- In l...
> ,
> > > Triffid Hunter
> > > > LPC17xx is a von-neumann architecture chip. This means that it
> has one
> > > > memory space into which both flash and ram are mapped. As a result,
> > > > code can be run directly from flash, or loaded into ram and run from
> > > > there.
> > >
> > >
> >
> >
> >
> >
> >



Salam Amr
Thank you so much. that is very useful and helpful. I couldn't open your link but I found your program from sourceforge site.

--- In l..., Amr Bekhit wrote:
>
> Salaam Yousefi,
>
> If you're looking for an alternative to the Keil Configuration Wizard, have
> a look at my own CMSIS Configuration Wizard, which you can find at
> helmpcb.com/software/cmsis-configuration-wizard.
>
> Amr
>
>

Il 26/08/2012 22:21, Mohammad ha scritto:
>
>
> Thanks for your lucid explanation.
> I just started to work with ARM processor. would you please give me
> some resources or links for using CMSIS?
>
CMSIS is a standard established by ARM with the intent of standardize a
minimum library (this written by ARM) to simplify the startup of the
Cortex based microcontrollers and the standard peripherals part of the
minimum set delivered with Cortex cores. So, to find and read the
general documentation about CMSIS you should register on the ARM web
site. Also at
http://www.keil.com/support/man/docs/gsac/gsac_cmsisoverview.htm you can
find useful informations but best of all you could visit www.onarm.com

But take care that ARM "imposes" silicon vendors to realize a library
following CMSIS guidelines to be CMSIS compliant, so it should be a 2
learning steps, one for the general ARM CMSIS implementation and the
other for the silicon vendor implementation.

Of course if you need just to use a CMSIS implementation you should use
that delivered by the silicon vendor and take care that you may find
some little differencies also between 2 CMSIS implementations related to
2 different microcontrollers also if they are made by the same silicon
vendor.
> --- In l... , "M.
> Manca" wrote:
> >
> > Il 26/08/2012 15:09, Mohammad ha scritto:
> > >
> > >
> > > Thanks for your reply Triffid, However in the datasheet says: "The ARM
> > > Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard
> > > architecture with separate local instruction and data buses as well as
> > > a third bus for peripherals" but the linker's has different linker
> > > configuration file as you told me.
> > >
> > Yes, correct it is an Harvard but it uses AHB bus (AMBA High performance
> > Bus) so it is the bus that makes possible to execute the code also from
> > memory that should be devoted only to data space.
> > So ARM cores are more then a CPU core are a complex architecture made of
> > several simple bricks that all together made probably the best
> > microcontroller architecture seen in the world until now.
> > >
> > >
> > > --- In l...
> ,
> > > Triffid Hunter
> > > > LPC17xx is a von-neumann architecture chip. This means that it
> has one
> > > > memory space into which both flash and ram are mapped. As a result,
> > > > code can be run directly from flash, or loaded into ram and run from
> > > > there.
> > >
> > >
> >
> >
> >
> >
> >