Don't understand why the required memory access time is much shorter
than it can be from the external bus sequences figures.
For example, in LPC2292/LC2294 User manual, for the external memory
read access, if XCLK is 50MHz and WST1=0 (1 wait state). If we use
philips' formula, Tram <= Tcyc*(2 + WST1)-20ns, the result is 20ns,
which means a 20ns access time memory is require for the 50MHz XCLK
operation. But when looking at the read access timing diagram, with
WST1=0, 3 XCLK clocks are used to finish one read access. That's a
total of 60ns. A 60ns memory is enough for this situation, why
philips requires a 20ns device?