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LPC2294 External Bus Speed

Started by itsjustimpossible July 4, 2005
Hi
There have been a few messages about this, but I can't find anything
explicit so I thought I would ask a quick question.

In an FIQ I need to transfer 15 bytes to an external device in less
than 1uS.

Is this possible? Unless I am completely off track (probable), it
looks like it should be.

The bus is 8-bit with no wait states. We are using the PLL to give a
60MHz core clock and the peripheral clock is set equal to the core
clock. The MAM is enabled.

I can't seem to achieve anywhere near this figure.

Any thoughts would be greatly appreciated.

many thanks
Simon


An Engineer's Guide to the LPC2100 Series

--- In lpc2000@lpc2..., "itsjustimpossible" <simonjh@b...> wrote:

I would like to clarify your request.

> Hi
> There have been a few messages about this, but I can't find anything
> explicit so I thought I would ask a quick question.
>
> In an FIQ I need to transfer 15 bytes to an external device in less
> than 1uS.
>

Does this mean :

1) " Start transfering 15 with 1uS after the edge that causes FIQ"
2) " Finish 15 bytes with in 1 uS after the edge that causes FIQ" > Is this possible? Unless I am completely off track (probable), it
> looks like it should be.
>

As you can see the timing of these two cases is very dramatic. > The bus is 8-bit with no wait states. We are using the PLL to give a
> 60MHz core clock and the peripheral clock is set equal to the core
> clock. The MAM is enabled.
>
> I can't seem to achieve anywhere near this figure.
>
> Any thoughts would be greatly appreciated.
>
> many thanks
> Simo


Thanks

donhamilton



Hi
In an ideal world I would like to achieve number 2...

2) " Finish 15 bytes with in 1 uS after the edge that causes FIQ"

However I appreciate that may be a tall order when taking interrupt
latency into account.

At a push I would settle with being able to transfer 15 bytes in
less than 1uS. Not including the interrupt latency of the FIQ.

best regards
Simon

--- In lpc2000@lpc2..., "donhamilton2002" <hamilton@d...>
wrote:
> --- In lpc2000@lpc2..., "itsjustimpossible" <simonjh@b...>
wrote:
>
> I would like to clarify your request.
>
> > Hi
> > There have been a few messages about this, but I can't find
anything
> > explicit so I thought I would ask a quick question.
> >
> > In an FIQ I need to transfer 15 bytes to an external device in
less
> > than 1uS.
> >
>
> Does this mean :
>
> 1) " Start transfering 15 with 1uS after the edge that causes
FIQ"
> 2) " Finish 15 bytes with in 1 uS after the edge that causes
FIQ"
>
>
> > Is this possible? Unless I am completely off track (probable),
it
> > looks like it should be.
> >
>
> As you can see the timing of these two cases is very dramatic. > > The bus is 8-bit with no wait states. We are using the PLL to
give a
> > 60MHz core clock and the peripheral clock is set equal to the
core
> > clock. The MAM is enabled.
> >
> > I can't seem to achieve anywhere near this figure.
> >
> > Any thoughts would be greatly appreciated.
> >
> > many thanks
> > Simo > Thanks
>
> donhamilton



Gentleman,
look at your BCFG value. it determines our read/write and wait state and idle time between two read/write ...
You have to minimize this as you requirement is 15 byte per microsecond measns 66ns per byte time...
k b shah
----- Original Message -----
From: itsjustimpossible
To: lpc2000@lpc2...
Sent: Tuesday, July 05, 2005 4:29 AM
Subject: [lpc2000] Re: LPC2294 External Bus Speed Hi
In an ideal world I would like to achieve number 2...

2) " Finish 15 bytes with in 1 uS after the edge that causes FIQ"

However I appreciate that may be a tall order when taking interrupt
latency into account.

At a push I would settle with being able to transfer 15 bytes in
less than 1uS. Not including the interrupt latency of the FIQ.

best regards
Simon

--- In lpc2000@lpc2..., "donhamilton2002" <hamilton@d...>
wrote:
> --- In lpc2000@lpc2..., "itsjustimpossible" <simonjh@b...>
wrote:
>
> I would like to clarify your request.
>
> > Hi
> > There have been a few messages about this, but I can't find
anything
> > explicit so I thought I would ask a quick question.
> >
> > In an FIQ I need to transfer 15 bytes to an external device in
less
> > than 1uS.
> >
>
> Does this mean :
>
> 1) " Start transfering 15 with 1uS after the edge that causes
FIQ"
> 2) " Finish 15 bytes with in 1 uS after the edge that causes
FIQ"
>
>
> > Is this possible? Unless I am completely off track (probable),
it
> > looks like it should be.
> >
>
> As you can see the timing of these two cases is very dramatic. > > The bus is 8-bit with no wait states. We are using the PLL to
give a
> > 60MHz core clock and the peripheral clock is set equal to the
core
> > clock. The MAM is enabled.
> >
> > I can't seem to achieve anywhere near this figure.
> >
> > Any thoughts would be greatly appreciated.
> >
> > many thanks
> > Simo > Thanks
>
> donhamilton


------
YAHOO! GROUPS LINKS

a.. ------


Hi
Thanks for the suggestion but we already have it configured with zero
wait states etc. So the bus should be running as fast as possible.

I have been doing some experiments today and I think the bus access is
probably OK. I think the main source of delay is the interrupt latency
of the FIQ which seems to be about 800nS.

There is also some jitter on that, so all together I am not sure if
the ARM7 is capable of doing what I need in this instance.

Bit of a shame

Best regards
Simon

--- In lpc2000@lpc2..., "k b shah \(lascaux\)" <kbshah@l...>
wrote:
> Gentleman,
> look at your BCFG value. it determines our read/write and wait state
and idle time between two read/write ...
> You have to minimize this as you requirement is 15 byte per
microsecond measns 66ns per byte time...
> k b shah




> of the FIQ which seems to be about 800nS.
>
> There is also some jitter on that, so all together I am not sure if
> the ARM7 is capable of doing what I need in this instance.
>
> Bit of a shame
> Simon
>

> 15 byte per microsecond measns 66ns per byte time...


Simon,

This pushes the software solution. A small FPGA would get this done.
I am sure you are calculating the 15 bytes well in advance of the FIQ.

Pre-loading the 15 byte into the memory of the FPGA, arm the FPGA
logic and wait for the FIQ. The FIQ will also tell the ARM7 that the
data has been transfered, so the next 15 bytes can be pre-loaded
for the next FIQ.

donhamilton

PS: This is why I love embedded work. Creative solutions to unusal
problems.