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FIQ tuning

Started by 42Bastian Schick July 26, 2005
Hi,

while investigating the max. FIQ latency on a LPC2294 (other LPC should
be similar), I wrote following code which fits completly into the
vector table and allows a total of 7 (or 5 with synchronisation with
an RTOS or higher layer) instructions to be executed without a branch.

It uses vectaddr14 and vectaddr15 of the VIC to store the Abort and
Undefined Handler addresses.

I used EXTINT1 to trigger interrupts.

.section .init,"ax"
.align 2
.code 32

.extern Undefined_Handler
.extern Abort_Handler
.extern Prefetch_Handler

@ Start Vector
VectorTable:
Undefined_Addr: .long Undefined_Handler // reset-vector, not used
LDR PC, Undefined_Addr
LDR PC, SWI_Addr
LDR PC, [pc,#-0xedc] // Prefetch_Addr (0xfffff138, vectaddr14)
LDR PC, [pc,#-0xedc] // Abort_Addr (0xfffff13c, vectaddr15)
SWI_Addr: .long sc_sysSWI // reserved vector
ldr pc, [pc, #-0xff0] // IRQ
nop
nop
nop
nop
nop
/*
** synchronise SCIOPTA world via soft irq every 32 FIQ
*/
adds r8,r8,#0x08000000
streq r10,[r9,#0x18] // _VIC_SOFTINT = 1

str r10,[r11,#0] // EXTINT1
subs pc,lr,#4 // return to interrupted function

To extend this, more code has to be linked to the flash at 0x40.

The setup looks like this:
MSR cpsr_c,#PSR_FIQ_MODE|PSR_I_BIT|PSR_F_BIT
ldr r13,=0xe0028000 // no FIQ stack,so r13 is GP register
mov r12,#0x104 // scrath registers

ldr r11,=0xe01fc140 // EXTINT
mov r10,#2 // EINT1
mvn r9,#0
mov r9,r9,lsl #12 // r9 = VIC-base == 0xfffff000
mov r8,#0 // used to synchronize

mov r1,#0x4000
str r1,[r9,#0x0c] // EINT1 == FIQ
str r1,[r9,#0x10] // enable EINT1

ldr r1,=Prefetch_Handler
str r1,[r9,#0x138]
ldr r1,ort_Handler
str r1,[r9,#0x13c] Ah, and I found a latency of max. 400ns (VPB == CPU == 60MHz),
which is 24 cycles. Strangely I found a jitter of 50ns even if nothing
else is running.

--
42Bastian Schick



An Engineer's Guide to the LPC2100 Series