UART1 and FIFO Reset (ISSUE)

Started by genie_23432 August 3, 2005

After much fustration I appear to have solved most of my stability
issues (although not all of them). I seem to have an undocumented
issue with UART1 on the LPC2119 and was wondering if anyone else ran
into the same problem. At the very least I figure I would warn
people about the potential issue since I couldn't find it in the
current errata.

It appears that using the RX FIFO Reset when running at highspeed
(over 100Kbps) that the behavior of the UART is very unpredictable.
I believe it might also exist at slower speeds although less often.
In my application I wanted to flush the FIFO when any error occured
so that I could try and more quickly resync on the data and avoid
reading corrupted data. As stated using the FIFO reset cause
unpredictable behavior such as: having the THRE interrupt ignored,
having the UART FIFO randomly being disabled, and having a character
time-out indicator interrupt I could not clear even though the
receive data ready bit said no data was in the fifo.

Unfortuantly I do not have too much time to investigate this
behaviour at this time since I wasted well over a week on this
project trying to solve my serial issues. All I know for sure is
that changing nothing in the code except for removing the FIFO reset
line solved over 90% of my issues. I still have some other issues
that may be related to the UART but I have not been able to confirm
this. I will be contacting Phillips in regards to this issue to see
what they have to say.


An Engineer's Guide to the LPC2100 Series