SSP FIFO

Started by medw...@... September 2, 2005

...of course when I say that the manual doesn't mention the size of the SSP FIFo I'm obviously ignoring the very first page describing the SSP Features where it says there is 8-frame FIFOs for both transmit and receive!!! Doh.

Note to self, when searching manuals include FIFOs as well as FIFO in whole word searches.... ;-)

Have I made a similar blunder in configuring the SPI0 SCK? (still no clock).

Sheepish regards,

Malcom



An Engineer's Guide to the LPC2100 Series

Hello Malcom,

Here are elements of your SPI0 code that are not lined up with this
peripheral's spec published in the LPC214x User Manual:

1)S0SPCCR = 0x000000FF;

The S0SPCCR register description specifies: "The value of this
register must always be an even number. As a result, bit 0 must
always be 0. The value of the register must also always be greater
than or equal to 8. Violations of this can result in unpredictable
behavior."

2) S0SPDR = 0x5555;

First, let's cover a couple of minor issues here: since you have
selected an 8 bit data frame (bit 2 in S0SPCR equals 0), there is no
reason to write something to bits 15 to 8 in S0SPDR since this
content corresponds only to bits in frames wider than you have
selected. Also, you are referring to "SOSPDR" in your post
8702 and
not to "S0SPDR" seems to be a typo.

Now, the key issue with the way you used the S0SPDR register is that
you have never read the S0SPSR register once you have written
something into the data register. As it is specified in the S0SPDR
register description: "When a master, a write to this register
will
start a SPI data transfer. Writes to this register will be blocked
from when a data transfer starts to when the SPIF status bit is set,
and the status register has not been read."

Therefore, once you have written data into the S0SPDR register, you
must read the S0SPSR register with the SPIF bit set before you write
to the S0SPDR register again.

Here is an example based on your code that shows SPI0 master mode
operational:

volatile unsigned char spi_stat;
volatile unsigned int spi_data;

void main (void) {

// PINSEL0 = 0x00005500; // SPI Pins - SSEL0 needs pull-up (1)
PINSEL0 = 0x00001500; // SPI Pins - no pull-up on SSEL0 (2)
IODIR0 = 0x00000400; // Chipselect
S0SPCCR = 0x08; // SPI prescaler must be even >=8
S0SPCR = 0x0020; // Master, CPOL=0, CPHA=0, 8 bits
spi_stat = S0SPSR; // Clear status register flags...
spi_data = S0SPDR; // ... with accessing data register

while(1){
IOCLR0 = 0x00000400; //select slave
S0SPDR = 0x0055; //send data to slave
while((S0SPSR&0x80)==0x00); //wait for transfer to finish
IOSET0 = 0x00000400; //deselect slave
}
}

At the end, if your LPC214x is the only SPI master in the system,
there is no need for the SSEL0 line to be configured as a SPI0
pin/signal and pulled high. This feature is documented in the SSEL0
pin description and demonstrated in the code above.

We hope this will help you in debugging your application.

Regards,

Philips Apps Team --- In lpc2000@lpc2..., medwar19@h... wrote:
>
> ...of course when I say that the manual doesn't mention the size
of the SSP FIFo I'm obviously ignoring the very first page
describing the SSP Features where it says there is 8-frame FIFOs for
both transmit and receive!!! Doh.
>
> Note to self, when searching manuals include FIFOs as well as FIFO
in whole word searches.... ;-)
>
> Have I made a similar blunder in configuring the SPI0 SCK? (still
no clock).
>
> Sheepish regards,
>
> Malcom