Forums

lpc2103 manual

Started by Gus October 12, 2005
Any updates on the manual of LPC2103?
Any info on the pinout of LPC2103 PLCC44?
If not, when will this data be available?

Thanks,

Gus



An Engineer's Guide to the LPC2100 Series

Hello Gus,

the Users Manual will be available with the samples in November. The
PLCC-44 pinout turned out to be a less restricted than previously
assumed. I will post it as a jpg-file in the files section today.

We combined the pins VBAT and V18 and made it just a V18. This limits
the ability to buffer the RealTimeClock with a battery but if the
device is in power down mode with V18 applied, the RTC will keep
running and the RAM contents remains. Current in power down is
expected typically in the 10 uAs range.

Given the specified power consumption of the I/O pins, we decided to
eliminate one Vdd3 that was pin 17 on the TQFP-48 package. As a
result, high levels of pins 18 through 28 of the PLCC package might be
0.1V lower than those on the side of pin 1. All are well within
specified levels.

Given the input from this Forum and checking with our partners
providing debuggers, one JTAG signal, the return clock was sacrificed.
The RTCK is most important if JTAG needs to adapt to changing clock
speeds. Our recommendation is to use a JTAG clock of 1 MHz which
covers all speeds from 10 MHz to 70 MHz CPU.

Last but not least the only "funtional pin" we had to eliminate was
the AIN7, pin 39 on the TQFP-48.

Hope this will not upset too many people and provide maximum
functionality for most of us.

Regards, Robert

--- In lpc2000@lpc2..., "Gus" <gus_is_working@y...> wrote:
>
> Any updates on the manual of LPC2103?
> Any info on the pinout of LPC2103 PLCC44?
> If not, when will this data be available?
>
> Thanks,
>
> Gus
>




Great!!! Thanks for the pinout.

If no manual exists yet, can we get some info on DEBUG pin? Is this
used to enable JTAG or to enter boot loader? is P0.14 still used to
enter boot loader?

Also, can TRST pin be used as I/O while other JTAG pins are running
JTAG? Am I crazy to ask this? :-)

Gus
--- In lpc2000@lpc2..., "philips_apps" <philips_apps@y...>
wrote:
>
> Hello Gus,
>
> the Users Manual will be available with the samples in November.
The
> PLCC-44 pinout turned out to be a less restricted than previously
> assumed. I will post it as a jpg-file in the files section today.
>
> We combined the pins VBAT and V18 and made it just a V18. This
limits
> the ability to buffer the RealTimeClock with a battery but if the
> device is in power down mode with V18 applied, the RTC will keep
> running and the RAM contents remains. Current in power down is
> expected typically in the 10 uAs range.
>
> Given the specified power consumption of the I/O pins, we decided
to
> eliminate one Vdd3 that was pin 17 on the TQFP-48 package. As a
> result, high levels of pins 18 through 28 of the PLCC package
might be
> 0.1V lower than those on the side of pin 1. All are well within
> specified levels.
>
> Given the input from this Forum and checking with our partners
> providing debuggers, one JTAG signal, the return clock was
sacrificed.
> The RTCK is most important if JTAG needs to adapt to changing
clock
> speeds. Our recommendation is to use a JTAG clock of 1 MHz which
> covers all speeds from 10 MHz to 70 MHz CPU.
>
> Last but not least the only "funtional pin" we had to eliminate
was
> the AIN7, pin 39 on the TQFP-48.
>
> Hope this will not upset too many people and provide maximum
> functionality for most of us.
>
> Regards, Robert
>
> --- In lpc2000@lpc2..., "Gus" <gus_is_working@y...> wrote:
> >
> > Any updates on the manual of LPC2103?
> > Any info on the pinout of LPC2103 PLCC44?
> > If not, when will this data be available?
> >
> > Thanks,
> >
> > Gus
> >
>




Gus

One of the goals was to keep the 2103 as compatible as possible to
the LPC2104/5/6. DBSEL will enable JTAG (located on the pins of the
former secondary JTAG), but 0.14 is still needed for ISP entry.
TRST is part of the JTAG while enabling it, sorry, can not be used
as GPIO while using JTAG.

Robert

--- In lpc2000@lpc2..., "Gus" <gus_is_working@y...> wrote:
>
> Great!!! Thanks for the pinout.
>
> If no manual exists yet, can we get some info on DEBUG pin? Is
this
> used to enable JTAG or to enter boot loader? is P0.14 still used
to
> enter boot loader?
>
> Also, can TRST pin be used as I/O while other JTAG pins are
running
> JTAG? Am I crazy to ask this? :-)
>
> Gus
> --- In lpc2000@lpc2..., "philips_apps" <philips_apps@y...>
> wrote:
> >
> > Hello Gus,
> >
> > the Users Manual will be available with the samples in November.
> The
> > PLCC-44 pinout turned out to be a less restricted than
previously
> > assumed. I will post it as a jpg-file in the files section
today.
> >
> > We combined the pins VBAT and V18 and made it just a V18. This
> limits
> > the ability to buffer the RealTimeClock with a battery but if
the
> > device is in power down mode with V18 applied, the RTC will keep
> > running and the RAM contents remains. Current in power down is
> > expected typically in the 10 uAs range.
> >
> > Given the specified power consumption of the I/O pins, we
decided
> to
> > eliminate one Vdd3 that was pin 17 on the TQFP-48 package. As a
> > result, high levels of pins 18 through 28 of the PLCC package
> might be
> > 0.1V lower than those on the side of pin 1. All are well within
> > specified levels.
> >
> > Given the input from this Forum and checking with our partners
> > providing debuggers, one JTAG signal, the return clock was
> sacrificed.
> > The RTCK is most important if JTAG needs to adapt to changing
> clock
> > speeds. Our recommendation is to use a JTAG clock of 1 MHz which
> > covers all speeds from 10 MHz to 70 MHz CPU.
> >
> > Last but not least the only "funtional pin" we had to eliminate
> was
> > the AIN7, pin 39 on the TQFP-48.
> >
> > Hope this will not upset too many people and provide maximum
> > functionality for most of us.
> >
> > Regards, Robert
> >
> > --- In lpc2000@lpc2..., "Gus" <gus_is_working@y...>
wrote:
> > >
> > > Any updates on the manual of LPC2103?
> > > Any info on the pinout of LPC2103 PLCC44?
> > > If not, when will this data be available?
> > >
> > > Thanks,
> > >
> > > Gus
> > >
> >
>




Well done Philips - that is an excellent compromise and certainly a
better than I expected!

With Kind Regards, David Kay

Tel : +64 9 974 2207
Mob: +64 21 664 351
Email : <mailto:david.kay@davi...> david.kay@davi...
-----Original Message-----
From: lpc2000@lpc2... [mailto:lpc2000@lpc2...] On Behalf
Of philips_apps
Sent: Thursday, 13 October 2005 5:38 a.m.
To: lpc2000@lpc2...
Subject: [lpc2000] Re: lpc2103 manual -- PLCC44 pinout see files
sections

Hello Gus,

the Users Manual will be available with the samples in November. The
PLCC-44 pinout turned out to be a less restricted than previously
assumed. I will post it as a jpg-file in the files section today.

We combined the pins VBAT and V18 and made it just a V18. This limits
the ability to buffer the RealTimeClock with a battery but if the
device is in power down mode with V18 applied, the RTC will keep
running and the RAM contents remains. Current in power down is
expected typically in the 10 uAs range.

Given the specified power consumption of the I/O pins, we decided to
eliminate one Vdd3 that was pin 17 on the TQFP-48 package. As a
result, high levels of pins 18 through 28 of the PLCC package might be
0.1V lower than those on the side of pin 1. All are well within
specified levels.

Given the input from this Forum and checking with our partners
providing debuggers, one JTAG signal, the return clock was sacrificed.
The RTCK is most important if JTAG needs to adapt to changing clock
speeds. Our recommendation is to use a JTAG clock of 1 MHz which
covers all speeds from 10 MHz to 70 MHz CPU.

Last but not least the only "funtional pin" we had to eliminate was
the AIN7, pin 39 on the TQFP-48.

Hope this will not upset too many people and provide maximum
functionality for most of us.

Regards, Robert

--- In lpc2000@lpc2..., "Gus" <gus_is_working@y...> wrote:
>
> Any updates on the manual of LPC2103?
> Any info on the pinout of LPC2103 PLCC44?
> If not, when will this data be available?
>
> Thanks,
>
> Gus
>
_____

> Terms of Service.

_____


philips_apps wrote:

>Gus
>
>One of the goals was to keep the 2103 as compatible as possible to
>the LPC2104/5/6. DBSEL will enable JTAG (located on the pins of the
>former secondary JTAG), but 0.14 is still needed for ISP entry.
>TRST is part of the JTAG while enabling it, sorry, can not be used
>as GPIO while using JTAG.
Lots of debuggers work without using nTRST.

According to http://www.arm.com/support/faqdev/4182.html.

"The difference is that with TCK and TMS only the TAP controller is
reset, while nTRST also resets the Embedded-ICE logic in the core, which
clears any existing breakpoints or watchpoints."

Assuming that the first part of this statement is true (I'm not
convinced) can someone explain the scenario in which the debug registers
are defined but the TAP isn't connected.

Regards
Michael

>Robert
>
>--- In lpc2000@lpc2..., "Gus" <gus_is_working@y...> wrote: >>Great!!! Thanks for the pinout.
>>
>>If no manual exists yet, can we get some info on DEBUG pin? Is
>>
>>
>this >>used to enable JTAG or to enter boot loader? is P0.14 still used
>>
>>
>to >>enter boot loader?
>>
>>Also, can TRST pin be used as I/O while other JTAG pins are
>>
>>
>running >>JTAG? Am I crazy to ask this? :-)
>>
>>Gus
>>--- In lpc2000@lpc2..., "philips_apps" <philips_apps@y...>
>>wrote:
>>
>>
>>>Hello Gus,
>>>
>>>the Users Manual will be available with the samples in November.
>>>
>>>
>>The
>>
>>
>>>PLCC-44 pinout turned out to be a less restricted than
>>>
>>>
>previously >>>assumed. I will post it as a jpg-file in the files section
>>>
>>>
>today. >>>We combined the pins VBAT and V18 and made it just a V18. This
>>>
>>>
>>limits
>>
>>
>>>the ability to buffer the RealTimeClock with a battery but if
>>>
>>>
>the >>>device is in power down mode with V18 applied, the RTC will keep
>>>running and the RAM contents remains. Current in power down is
>>>expected typically in the 10 uAs range.
>>>
>>>Given the specified power consumption of the I/O pins, we
>>>
>>>
>decided >>to
>>
>>
>>>eliminate one Vdd3 that was pin 17 on the TQFP-48 package. As a
>>>result, high levels of pins 18 through 28 of the PLCC package
>>>
>>>
>>might be
>>
>>
>>>0.1V lower than those on the side of pin 1. All are well within
>>>specified levels.
>>>
>>>Given the input from this Forum and checking with our partners
>>>providing debuggers, one JTAG signal, the return clock was
>>>
>>>
>>sacrificed.
>>
>>
>>>The RTCK is most important if JTAG needs to adapt to changing
>>>
>>>
>>clock
>>
>>
>>>speeds. Our recommendation is to use a JTAG clock of 1 MHz which
>>>covers all speeds from 10 MHz to 70 MHz CPU.
>>>
>>>Last but not least the only "funtional pin" we had to eliminate
>>>
>>>
>>was
>>
>>
>>>the AIN7, pin 39 on the TQFP-48.
>>>
>>>Hope this will not upset too many people and provide maximum
>>>functionality for most of us.
>>>
>>>Regards, Robert
>>>
>>>--- In lpc2000@lpc2..., "Gus" <gus_is_working@y...>
>>>
>>>
>wrote: >>>>Any updates on the manual of LPC2103?
>>>>Any info on the pinout of LPC2103 PLCC44?
>>>>If not, when will this data be available?
>>>>
>>>>Thanks,
>>>>
>>>>Gus
>>>>
>>>>
>>> >Yahoo! Groups Links >




When will the manual come for LPC2103?

Gus

--- In lpc2000@lpc2..., "Gus" <gus_is_working@y...> wrote:
>
> Great!!! Thanks for the pinout.
>
> If no manual exists yet, can we get some info on DEBUG pin? Is
this
> used to enable JTAG or to enter boot loader? is P0.14 still used
to
> enter boot loader?
>
> Also, can TRST pin be used as I/O while other JTAG pins are
running
> JTAG? Am I crazy to ask this? :-)
>
> Gus
> --- In lpc2000@lpc2..., "philips_apps" <philips_apps@y...>
> wrote:
> >
> > Hello Gus,
> >
> > the Users Manual will be available with the samples in November.
> The
> > PLCC-44 pinout turned out to be a less restricted than
previously
> > assumed. I will post it as a jpg-file in the files section
today.
> >
> > We combined the pins VBAT and V18 and made it just a V18. This
> limits
> > the ability to buffer the RealTimeClock with a battery but if
the
> > device is in power down mode with V18 applied, the RTC will keep
> > running and the RAM contents remains. Current in power down is
> > expected typically in the 10 uAs range.
> >
> > Given the specified power consumption of the I/O pins, we
decided
> to
> > eliminate one Vdd3 that was pin 17 on the TQFP-48 package. As a
> > result, high levels of pins 18 through 28 of the PLCC package
> might be
> > 0.1V lower than those on the side of pin 1. All are well within
> > specified levels.
> >
> > Given the input from this Forum and checking with our partners
> > providing debuggers, one JTAG signal, the return clock was
> sacrificed.
> > The RTCK is most important if JTAG needs to adapt to changing
> clock
> > speeds. Our recommendation is to use a JTAG clock of 1 MHz which
> > covers all speeds from 10 MHz to 70 MHz CPU.
> >
> > Last but not least the only "funtional pin" we had to eliminate
> was
> > the AIN7, pin 39 on the TQFP-48.
> >
> > Hope this will not upset too many people and provide maximum
> > functionality for most of us.
> >
> > Regards, Robert
> >
> > --- In lpc2000@lpc2..., "Gus" <gus_is_working@y...>
wrote:
> > >
> > > Any updates on the manual of LPC2103?
> > > Any info on the pinout of LPC2103 PLCC44?
> > > If not, when will this data be available?
> > >
> > > Thanks,
> > >
> > > Gus
> > >
> >
>