Dear all,

I have a problem to setup the MCLK and SMCLK with FLL+
for MSP430F413, would you give me a help?

The following is the code that I used to test the
MCLK/SMCLK setting. I just try to setup the clock and
then output it to P1.5 and P1.1 to check the
frequency.
And actually, I need a ~2 MHz MCLK


void main( void )
{
	WDTCTL = WDTPW + WDTHOLD;					// stop watchdog timer
	SCFI0 |= FN_4;								// DCO conter at 2 MHz
	SCFQCTL = 31;								// f(DCOCLK) = 2 * 32768 * ( 31
+ 1 ) ~= 2.097 MHz
	FLL_CTL0 = DCOPLUS + XCAP18PF;				// DCO+ = 1;
	P1SEL = 0x22;
	P1DIR = 0x22;

	while( 1 );
}

The problem I had is that the above code runs but,

1) If I set FN_4, then according to the spec. the
fnomial min is 2.1MHz@3V and TAP2. It's too fast.
2) So, I try to use FN_3, then the fnomial is ~2MHz.
But in this case, the CSPY is a little out of control.
	- Whenever debugger start, programme auto load and
run, and the source code windows is bank.
	- The output frequency signal from P1.1 and P1.5 is
not normal. It just last for ~400uS then it stop and
then report again. It seems the MCU is reset.

I am using IAR 1.26B evaluation version with T.I. FET.

I am totally in chaos, would someone can help?


have a good day
Ken

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