Hello.

I'm using an MSP430F147 connected to an Atmel Mega128L via 4 wire 
SPI.  To date, I have been unable to get the 'F147 to act as a 
reliable slave.  If the clock line ever glitches (which it can do as 
the Mega128L comes up.  The 'F147 is already running), there is no 
way to tell the MSP430 to resync the SPI circuitry.

All SPI implementations I've ever used before support the following 
functionality in one form or another: "The /SS pin is useful for 
packet/byte synchronization to keep the slave bit counter synchronous
with the master clock generator. When the /SS pin is driven high, the 
SPI slave will immediately reset the send and receive logic, and drop 
any partially received data in the Shift Register.".  This is from 
the Mega128L datasheet.

The MSP430 seems to not have this functionality.  In implementation, 
the /SS line acts as nothing more than an enabling gate for the 
clock.  This does mean that you could suspend communication to a part 
while on the SPI while you talk to another part, but I really don't 
think this is a common implementation at the byte level.  Packet 
level, possible, but interrupting a byte in transfer doesn't make any 
sense.  I cannot believe TI would be so thick as to obviously not 
support this.  A design bug I could see, but to deliberately design 
it otherwise?  How would you ever maintain sync?

I suppose that in theory you could use the /SS line as an interrupt 
input, but then you introduce race conditions, since the interrupt 
may not be able to be serviced before the SPI port can be reset.  And 
the technique just feels like a massive kludge.

I have solved this particular problem by doing a role reversal.  
Since the Mega128L correctly supports the /SS line implementation, 
the MSP430 can act as master.  It works, but I had planned to use the 
MSP430s as slaves in other projects.  Unless I can solve this 
gracefully, I'm going to use Atmel or Motorola parts instead.

In searching the archives, I've seen a mention of other people having 
problems, but there are no follow-up threads to them.  Is no one else 
using MSP430s as slaves in any projects?

--John

On Tue, 21 Jan 2003 13:49:19 -0000, you wrote:

>
>In searching the archives, I've seen a mention of other people having 
>problems, but there are no follow-up threads to them.  Is no one else 
>using MSP430s as slaves in any projects?

I'm using a F149 FET board as a SPI slave to a TMS320C5416 DSP, and
while I haven't seen the problem you describe I am having a problem
with data from the slave to the master (master to slave appears to be
working as expected).

When the MSP430 needs to talk to the DSP (which is master) I pre-load
a value into U0TXBUF, and then pull a port line low for the first byte
of the transfer. The DSP polls this line and starts a SPI transfer.

The problem is that the byte that the DSP reads is always an 0xFF. The
value that I load doesn't show up until the second byte transferred to
the DSP. This is a bit of a problem, since the first byte sent is
supposed to tell the DSP how many following bytes to transfer.

Has anyone else had problems like this with transferring data from the
slave to the master?

Thanks,

Brian

-----------------
Brian C. Lane (W7BCL)                      Programmer
www.shinemicro.com   RF, DSP & Microcontroller Design

On Wed, 29 Jan 2003 13:45:51 -0800, you wrote:

>On Tue, 21 Jan 2003 13:49:19 -0000, you wrote:
>
>>
>>In searching the archives, I've seen a mention of other people
having 
>>problems, but there are no follow-up threads to them.  Is no one else 
>>using MSP430s as slaves in any projects?
>
>I'm using a F149 FET board as a SPI slave to a TMS320C5416 DSP, and
>while I haven't seen the problem you describe I am having a problem
>with data from the slave to the master (master to slave appears to be
>working as expected).
>
>When the MSP430 needs to talk to the DSP (which is master) I pre-load
>a value into U0TXBUF, and then pull a port line low for the first byte
>of the transfer. The DSP polls this line and starts a SPI transfer.
>
>The problem is that the byte that the DSP reads is always an 0xFF. The
>value that I load doesn't show up until the second byte transferred to
>the DSP. This is a bit of a problem, since the first byte sent is
>supposed to tell the DSP how many following bytes to transfer.
>

Programmer error. I wasn't pulling !SS low for the transfer of the
first byte.

So for me SPI Slave (4 wire) is working fine.

Brian

-----------------
Brian C. Lane (W7BCL)                      Programmer
www.shinemicro.com   RF, DSP & Microcontroller Design

Brian,

    You should verify this by manually glitching the clock on the master,
then seeing if your data comes out like you think.  I imagine that unless
you're using some sort of external syncronization, you'll find that
you're a
bit or more off on every packet.  And hopefully, you're not trusting the
SPI
link to be intrinsically error free.  So if you do have a recovery
mechanism, you have to make sure you do something where some sequence sent
to the slave causes it to reset the SPI port, after it sees the clock line
idle for a few milliseconds.  Or some such similiar scheme.

    --John
  -----Original Message-----
  From: brian@bria... [mailto:brian@bria...]
  Sent: Wednesday, January 29, 2003 18:30
  To: msp430@msp4...
  Subject: Re: [msp430] SPI in slave role problem


  On Wed, 29 Jan 2003 13:45:51 -0800, you wrote:

  >On Tue, 21 Jan 2003 13:49:19 -0000, you wrote:
  >
  >>
  >>In searching the archives, I've seen a mention of other people
having
  >>problems, but there are no follow-up threads to them.  Is no one else
  >>using MSP430s as slaves in any projects?
  >
  >I'm using a F149 FET board as a SPI slave to a TMS320C5416 DSP, and
  >while I haven't seen the problem you describe I am having a problem
  >with data from the slave to the master (master to slave appears to be
  >working as expected).
  >
  >When the MSP430 needs to talk to the DSP (which is master) I pre-load
  >a value into U0TXBUF, and then pull a port line low for the first byte
  >of the transfer. The DSP polls this line and starts a SPI transfer.
  >
  >The problem is that the byte that the DSP reads is always an 0xFF. The
  >value that I load doesn't show up until the second byte transferred
to
  >the DSP. This is a bit of a problem, since the first byte sent is
  >supposed to tell the DSP how many following bytes to transfer.
  >

  Programmer error. I wasn't pulling !SS low for the transfer of the
  first byte.

  So for me SPI Slave (4 wire) is working fine.

  Brian

  -----------------
  Brian C. Lane (W7BCL)                      Programmer
  www.shinemicro.com   RF, DSP & Microcontroller Design

        




  .



  

On Wed, 29 Jan 2003 22:28:11 -0500, you wrote:

>Brian,
>
>    You should verify this by manually glitching the clock on the master,
>then seeing if your data comes out like you think.  I imagine that unless
>you're using some sort of external syncronization, you'll find
that you're a
>bit or more off on every packet.  And hopefully, you're not trusting
the SPI
>link to be intrinsically error free.  So if you do have a recovery
>mechanism, you have to make sure you do something where some sequence sent
>to the slave causes it to reset the SPI port, after it sees the clock line
>idle for a few milliseconds.  Or some such similiar scheme.

I just tried this. The setup is a F1232 FET board, ICC430 and NoICE
for development. I glitched the clock a few times and sent a few new
packets to it.

Using NoICE with breakpoints it is receiving just fine. The glitches
were done while !SS was high. Are you sure you have the MSP430 setup
for 4-wire mode? Maybe its still in 3-wire and the !SS line isn't
being used.

Brian
 
-----------------
Brian C. Lane (W7BCL)                      Programmer
www.shinemicro.com   RF, DSP & Microcontroller Design

    Pretty sure.  I spent quite a few hours on this problem, trying various
configurations.  And the docs for the F123 and F147 very clearly says it
suspends transactions, not resets the receiver logic (like the Atmel and
everyone else in the world).  I would suggest glitching with the -SS low,
and see if you can recover from that.

    In my system, the master maintains a continuous datastream to the slave.
This is the only way that the slave can talk back.  So even if the master
has nothing to say, it sends nulls.  And if the slave has something to say,
he just starts inserting bytes to be sent, otherwise he sends nulls.  The
only link between the two processors is a reset line (hardware reset), and
the SPI port.  The Mega128 (the master, in the original design) will reset
the F147, who will take variable amounts of time to wake up, depending on
the state of it's attache peripherials.  The Mega128 knows the F147 is
awake
when it starts talking back (by sending a "hello, world" type message.

    However, if the receiver is enable in mid-SPI byte, it gets horribly
horribly confused.  In a real SPI implementation (such as the Mega128 has),
when the -SS line went high between packets (or upon detection of a framing
error), the link would recover itself.  Since the F147 simply suspends the
clock, there's no way to have automagically in hardware reset the SPI
receiver and resync.

    By reversing the roles and making the F147 master, everything is fine.
As soon as the -SS lines goes high, the Mega128 resets the reciever, the SPI
clocks recover, then the packet protocol recovers.

    I consider this is a serious flaw in the SPI implementation of the F147.
And the problem becomes especially evident when you want to network a group
of F147 parts, since none of the implementations support clock recovery (at
least without a lot of code, and a highly likely race condition being
present.  SPI is only *supposed* to be 4 lines, not additional externals for
these kind of games).

    --John

  -----Original Message-----
  From: brian@bria... [mailto:brian@bria...]
  Sent: Thursday, January 30, 2003 13:49
  To: msp430@msp4...
  Subject: Re: [msp430] SPI in slave role problem


  On Wed, 29 Jan 2003 22:28:11 -0500, you wrote:

  >Brian,
  >
  >    You should verify this by manually glitching the clock on the master,
  >then seeing if your data comes out like you think.  I imagine that unless
  >you're using some sort of external syncronization, you'll find
that
you're a
  >bit or more off on every packet.  And hopefully, you're not trusting
the
SPI
  >link to be intrinsically error free.  So if you do have a recovery
  >mechanism, you have to make sure you do something where some sequence
sent
  >to the slave causes it to reset the SPI port, after it sees the clock
line
  >idle for a few milliseconds.  Or some such similiar scheme.

  I just tried this. The setup is a F1232 FET board, ICC430 and NoICE
  for development. I glitched the clock a few times and sent a few new
  packets to it.

  Using NoICE with breakpoints it is receiving just fine. The glitches
  were done while !SS was high. Are you sure you have the MSP430 setup
  for 4-wire mode? Maybe its still in 3-wire and the !SS line isn't
  being used.

  Brian

  -----------------
  Brian C. Lane (W7BCL)                      Programmer
  www.shinemicro.com   RF, DSP & Microcontroller Design

  .