Hi,

Is possible to pull the MCLK generated using DCO to an external pin
for viewing? The external pin may be a large load, and so may increase
the rise/fall times of the MCLK, but I just want to see that the MCLK
has a nice 50% duty cycle and is very clean and stable.

I read over the entire section regarding Basic Clock Module Operation,
but it did not mention anywhere that I can view the MCLK signal.

Seeing the MCLK is important because I believe the SPI Clock is
derived off of MCLK (or SMCLK I guess, but SMCLK is also off of MCLK),
and I have abnormalities in my SPI Clock. 

My SPI data is fine, but my SPI Clock signal is not so clean. To send
the 8 bits of SPI data at a time, the SPI Clock sometimes seems to
skip some pulses. So the Duty Cycle of the SPI Clock varies sometimes
from 30% to 70%, averaging around 50%. Sometimes the SPI_CLK low time
is longer, sometimes the SPI_CLK high time is longer.
Is it normal for the SPI_CLK to be like this? Or should it be a very
stable, constant 50% duty cycle on this SPI_CLK signal?


Thank you for your help,
Regards,
Richard

On larger devices, like the 149, MCLK is available as an output using 
the PxSEL register and PxDIR set to output for the relevant pin. This is 
P5.4 on the '149. On smaller devices like the 1121 the  MCLK is NOT 
directly available, however SMCLK is, in the same manner, but on P1.4

Al

finfets wrote:

>Hi,
>
>Is possible to pull the MCLK generated using DCO to an external pin
>for viewing? The external pin may be a large load, and so may increase
>the rise/fall times of the MCLK, but I just want to see that the MCLK
>has a nice 50% duty cycle and is very clean and stable.
>
>I read over the entire section regarding Basic Clock Module Operation,
>but it did not mention anywhere that I can view the MCLK signal.
>
>Seeing the MCLK is important because I believe the SPI Clock is
>derived off of MCLK (or SMCLK I guess, but SMCLK is also off of MCLK),
>and I have abnormalities in my SPI Clock. 
>
>My SPI data is fine, but my SPI Clock signal is not so clean. To send
>the 8 bits of SPI data at a time, the SPI Clock sometimes seems to
>skip some pulses. So the Duty Cycle of the SPI Clock varies sometimes
>from 30% to 70%, averaging around 50%. Sometimes the SPI_CLK low time
>is longer, sometimes the SPI_CLK high time is longer.
>Is it normal for the SPI_CLK to be like this? Or should it be a very
>stable, constant 50% duty cycle on this SPI_CLK signal?
>
>
>Thank you for your help,
>Regards,
>Richard
>
>
>
>
>.
>
> 
>Yahoo! Groups Links
>
>
>
> 
>
>
>
>
>  
>

Hi Al,

Great, thanks for the tips. I am using the MSP430F-1232.

Cheers,
Richard

--- In msp430@msp4..., Onestone <onestone@b...> wrote:
> On larger devices, like the 149, MCLK is available
as an output using 
> the PxSEL register and PxDIR set to output for the relevant pin.
This is 
> P5.4 on the '149. On smaller devices like the
1121 the  MCLK is NOT 
> directly available, however SMCLK is, in the same manner, but on P1.4
> 
> Al
> 
> finfets wrote:
> 
> >Hi,
> >
> >Is possible to pull the MCLK generated using DCO to an external pin
> >for viewing? The external pin may be a large load, and so may increase
> >the rise/fall times of the MCLK, but I just want to see that the MCLK
> >has a nice 50% duty cycle and is very clean and stable.
> >
> >I read over the entire section regarding Basic Clock Module Operation,
> >but it did not mention anywhere that I can view the MCLK signal.
> >
> >Seeing the MCLK is important because I believe the SPI Clock is
> >derived off of MCLK (or SMCLK I guess, but SMCLK is also off of MCLK),
> >and I have abnormalities in my SPI Clock. 
> >
> >My SPI data is fine, but my SPI Clock signal is not so clean. To send
> >the 8 bits of SPI data at a time, the SPI Clock sometimes seems to
> >skip some pulses. So the Duty Cycle of the SPI Clock varies sometimes
> >from 30% to 70%, averaging around 50%. Sometimes the SPI_CLK low time
> >is longer, sometimes the SPI_CLK high time is longer.
> >Is it normal for the SPI_CLK to be like this? Or should it be a very
> >stable, constant 50% duty cycle on this SPI_CLK signal?
> >
> >
> >Thank you for your help,
> >Regards,
> >Richard
> >
> >
> >
> >
> >.
> >
> > 
> >Yahoo! Groups Links
> >
> >
> >
> > 
> >
> >
> >
> >
> >  
> >