Hello, I'm trying to set up uart communication for receiving NMEA
messages from a GPS module. However it seems like the interrupt is
never being called. Here's the code I have to set up the UART
communication.
WDTCTL = WDTPW + WDTHOLD; // turn watch dog timer off
BCSCTL1 = 0x04; // ACLK = LFXT1 = LF XTAL
(32.768 kHz)
// This leaves XT2 on and
// able to be
// used for MCLK
do {
IFG1 &= ~OFIFG; // Clear OSCFault flag
for (i = 0xFF; i > 0; i--); // Time for flag to set
}
while ((IFG1 & OFIFG) == OFIFG); // OSCFault flag still set?
BCSCTL2 |= SELM1 + SELS; // MCLK = SMCLK = 7.3728 MHz
UCTL1 = CHAR + PENA; // 8 bit data, odd parity
// enabled
// UTCTL1 |= SSEL0 + SSEL1 + TXWAKE; // UCLK = SMCLK
UTCTL1 |= SSEL0 + SSEL1; // UCLK = SMCLK
// URCTL1 = URXEIE;
// 7.3728 MHz/9600 = 0768 = 0x0300
UBR01 = 0xc0;
UBR11 = 0x04;
UMCTL1 = 0x00; // no modulation because it
// divides evenly.
P3SEL |= 0x30; // P3.6,7 = USART0 TXD/RXD
P3DIR |= 0x10; // P3.6 output direction
P1DIR |= 0x10; // direction out on P1.4 GPS enable
P1OUT &= 0xEF; //enable P1.4 OE low for the GPS
ME2 |= UTXE1 + URXE1; // Enable USART0 TXD/RXD
IE2 |= URXIE1 + UTXIE1; // Enable USART0 RX/TX interrupt
_EINT(); // Enable interrupts
Does this look like the correct way to set up the uart?
Thanks,
Blake
setting up uart communication for 9600 baud rate
Started by ●May 30, 2003
Reply by ●May 30, 20032003-05-30
You're pretty close but some numbers are wrong. This code works for
the
449, so you'll need to change the port pins to match whatever chip you
have.
/* Uart 1 */
UCTL1 = CHAR|SWRST; // Set 8-bit character mode, leave
in reset
UTCTL1 = SSEL1; // UCLK = SMCLK
UBR01 = 0x00; // 7.3728MHz 9600 baud - 768 or 0x0300
UBR11 = 0x03; //
UMCTL1 = 0x00; // no modulation
ME2 |= (UTXE1 + URXE1); // Enable USART1 TXD/RXD
IE2 |= URXIE1; // Enable USART1 RX interrupt
IE2 |= UTXIE1; // Enable USART1 TX interrupt
URCTL1 |= URXEIE; // UART 1 Receive Control - Allow
error characters to set interrupt
P4SEL |= (SER_RX1_MASK|SER_TX1_MASK); // P4.0,1 = USART1 TXD/RXD
P4DIR |= (SER_TX1_MASK); // P4.0 output direction
UCTL1 &= ~SWRST; // Clear SWRST to enable uart
_EINT(); // Enable interrupts
Regards, Hugh
>Hello, I'm trying to set up uart communication for receiving NMEA
messages from a GPS module. However it seems like the interrupt is
never being called. Here's the code I have to set up the UART
communication.
WDTCTL = WDTPW + WDTHOLD; // turn watch dog timer off
BCSCTL1 = 0x04; // ACLK = LFXT1 = LF XTAL
(32.768 kHz)
// This leaves XT2 on and
// able to be
// used for MCLK
do {
IFG1 &= ~OFIFG; // Clear OSCFault flag
for (i = 0xFF; i > 0; i--); // Time for flag to set
}
while ((IFG1 & OFIFG) == OFIFG); // OSCFault flag still set?
BCSCTL2 |= SELM1 + SELS; // MCLK = SMCLK = 7.3728 MHz
UCTL1 = CHAR + PENA; // 8 bit data, odd parity
// enabled
// UTCTL1 |= SSEL0 + SSEL1 + TXWAKE; // UCLK = SMCLK
UTCTL1 |= SSEL0 + SSEL1; // UCLK = SMCLK
// URCTL1 = URXEIE;
// 7.3728 MHz/9600 = 0768 = 0x0300
UBR01 = 0xc0;
UBR11 = 0x04;
UMCTL1 = 0x00; // no modulation because it
// divides evenly.
P3SEL |= 0x30; // P3.6,7 = USART0 TXD/RXD
P3DIR |= 0x10; // P3.6 output direction
P1DIR |= 0x10; // direction out on P1.4 GPS enable
P1OUT &= 0xEF; //enable P1.4 OE low for the GPS
ME2 |= UTXE1 + URXE1; // Enable USART0 TXD/RXD
IE2 |= URXIE1 + UTXIE1; // Enable USART0 RX/TX interrupt
_EINT(); // Enable interrupts
Does this look like the correct way to set up the uart?
Thanks,
Blake
Reply by ●June 2, 20032003-06-02
Hugh, thanks for your help, but I still seem to be having some
problems. Does there seem to be anything wrong with the code below?
Using the MSP430F149.
int gps_config(void)
{
unsigned int i;
WDTCTL = WDTPW + WDTHOLD; // turn watch dog timer off
BCSCTL1 = 0x04; // ACLK = LFXT1 = LF XTAL (32.768 kHz)
// This leaves XT2 on and able to be
// used for MCLK
do {
IFG1 &= ~OFIFG; // Clear OSCFault flag
for (i = 0xFF; i > 0; i--); // Time for flag to set
}
while ((IFG1 & OFIFG) == OFIFG); // OSCFault flag still set?
// UCTL1 = CHAR + PENA; // 8 bit data, odd parity enabled
UCTL1 = (CHAR + PENA) + SWRST; // 8 bit data, odd parity enabled
//UTCTL1 |= SSEL0 + SSEL1 + TXWAKE;
UTCTL1 = SSEL1; // UCLK = SMCLK
//URCTL1 = URXEIE;
UBR01 = 0x00; // 7.3728MHz 9600 baud - 768 or 0x0300
UBR11 = 0x03; //
UMCTL1 = 0x00; // no modulation because it divides evenly.
ME2 |= UTXE1 + URXE1; // Enable USART1 TXD/RXD
IE2 |= URXIE1 + UTXIE1; // Enable USART1 RX/TX interrupt
URCTL1 |= URXEIE; // UART 1 Receive Control - Allow error
characters to set interrupt
P3SEL |= 0xc0; // P3.6,7 = USART1 TXD/RXD
P3DIR |= 0x40; // P3.6 output direction
P4DIR |= 0x20; //P4.5 GPS enable output direction
P4OUT &= 0xDF; //p4.5 GPS enable low
UCTL1 &= ~SWRST; // Clear SWRST to enable uart
_EINT(); // Enable interrupts
P2DIR |= 0x80; //turn on yellow LED light, for testing purposes
P2OUT &= 0x7F;
//send messages configuring the GPS
xmit_buffer(&PortConfigString, PortConfigStringLength);
for(i = 0; i<1000; i++){} //pause to give it time to process
xmit_buffer(&NMEAConfigString, NMEAConfigStringLength);
//loop to wait for interrupt
dollarflag = 0;
while(dollarflag != 1){
}
P4DIR |= 0x80; //turn on red LED light, for testing purposes
P4OUT &= 0x7F;
return 1;
}
--- In msp430@msp4..., Hugh Molesworth <nzbackpackers@y...>
wrote:
> You're pretty close but some numbers are wrong. This code works for
the
> 449, so you'll need to change the port pins
to match whatever chip
you have.
>
> /* Uart 1 */
>
> UCTL1 = CHAR|SWRST; // Set 8-bit character
mode, leave
> in reset
>
> UTCTL1 = SSEL1; // UCLK = SMCLK
>
> UBR01 = 0x00; // 7.3728MHz 9600 baud -
768 or 0x0300
> UBR11 = 0x03; //
> UMCTL1 = 0x00; // no modulation
>
> ME2 |= (UTXE1 + URXE1); // Enable USART1 TXD/RXD
> IE2 |= URXIE1; // Enable USART1 RX
interrupt
> IE2 |= UTXIE1; // Enable
USART1 TX
interrupt
> URCTL1 |= URXEIE; // UART 1
Receive Control -
Allow
> error characters to set interrupt
>
> P4SEL |= (SER_RX1_MASK|SER_TX1_MASK); // P4.0,1 = USART1
TXD/RXD
> P4DIR |= (SER_TX1_MASK); // P4.0
output direction
>
> UCTL1 &= ~SWRST; // Clear SWRST to enable
uart
>
> _EINT(); // Enable interrupts
>
> Regards, Hugh
>
> >Hello, I'm trying to set up uart communication for receiving NMEA
> messages from a GPS module. However it seems like the interrupt is
> never being called. Here's the code I have to set up the UART
> communication.
>
>
> WDTCTL = WDTPW + WDTHOLD; // turn watch dog timer off
>
>
> BCSCTL1 = 0x04; // ACLK = LFXT1 = LF XTAL
> (32.768 kHz)
> // This leaves XT2 on and
> // able to be
> // used for MCLK
> do {
> IFG1 &= ~OFIFG; // Clear OSCFault flag
> for (i = 0xFF; i > 0; i--); // Time for flag to set
> }
> while ((IFG1 & OFIFG) == OFIFG); // OSCFault flag still set?
>
> BCSCTL2 |= SELM1 + SELS; // MCLK = SMCLK = 7.3728
MHz
>
>
> UCTL1 = CHAR + PENA; // 8 bit data, odd parity
> // enabled
>
> // UTCTL1 |= SSEL0 + SSEL1 + TXWAKE; // UCLK = SMCLK
> UTCTL1 |= SSEL0 + SSEL1; // UCLK = SMCLK
> // URCTL1 = URXEIE;
>
> // 7.3728 MHz/9600 = 0768 = 0x0300
>
> UBR01 = 0xc0;
> UBR11 = 0x04;
> UMCTL1 = 0x00; // no modulation because it
> // divides evenly.
>
> P3SEL |= 0x30; // P3.6,7 = USART0 TXD/RXD
> P3DIR |= 0x10; // P3.6 output direction
> P1DIR |= 0x10; // direction out on P1.4 GPS enable
> P1OUT &= 0xEF; //enable P1.4 OE low for the GPS
>
> ME2 |= UTXE1 + URXE1; // Enable USART0 TXD/RXD
> IE2 |= URXIE1 + UTXIE1; // Enable USART0 RX/TX
interrupt
>
>
>
> _EINT(); // Enable interrupts
>
>
> Does this look like the correct way to set up the uart?
>
> Thanks,
> Blake
Reply by ●June 2, 20032003-06-02
Hi.
Doesn't look like you're setting up SMCLK. Here's some old
MSP430F149 code
I wrote which works fine, maybe you can see from this what the difference
is. I'm just about to leave for the airport so I hope that helps.
Regards, Hugh
void Start_Osc(void)
{
/*
* DCO is CR typically ?
*
* LFXT1CLK is typically 32.768kHz watch crystal used for low power.
*
* XT2CLK is typically 7.3728MHz crystal used for accurate high-speed comms.
*
* There are 3 system clock lines: ACLK, MCLK & SMCLK.
*
* Auxilliary clock ACLK is buffered LFXT1CLK divided by 1, 2, 4 or 8.
* Typically 32.768kHz watch crystal.
*
* Master clock MCLK is LFXT1CLK, XT2CLK or DCOCLK divided by 1, 2, 4 or 8.
*
* Submain clock SMCLK is LFXT1CLK, XT2CLK or DCOCLK divided by 1, 2, 4 or 8.
*/
WDTCTL = WDTPW + WDTHOLD; // Stop watchdog timer
IFG2 = 0; // Interrupt flag 2
IFG1 = 0; // Interrupt flag 1
/*
* Enable LFXT1CLK (typically 32.768kHz watch crystal used for low power)
*
* Enable XT2CLK (typically 7.3728MHz crystal used for accurate high-speed
comms)
*
*/
BCSCTL1 &= ~XT2OFF; // Enable XT2 crystal oscillator
BCSCTL1 &= ~XTS; // Enable low-frequency XT1 crystal
oscillator
do //wait in loop until crystal is stable
{
IFG1 &= ~OFIFG;
} while (OFIFG&IFG1);
Delay1();
IFG1 &= ~OFIFG; // Reset osc. fault flag again
/*
* DCO is CR typically ? let's go max speed
*
*/
DCOCTL |= DCO0 | DCO1 | DCO2; // Max speed for DCO!
/* Auxilliary clock ACLK is buffered LFXT1CLK divided by 1, 2, 4 or 8. */
BCSCTL1 &= ~(DIVA0|DIVA1); // Set DCO clock ACLK is buffered
LFXT1CLK divided by 1
/* Master clock MCLK is LFXT1CLK, XT2CLK or DCOCLK divided by 1, 2, 4 or 8. */
BCSCTL2 &= ~(DIVM1|DIVM0); /* Set Master clock MCLK to XT2CLK div 1 */
BCSCTL2 &= ~(SELM0); /* Set Master clock MCLK to XT2CLK div 1 */
BCSCTL2 |= (SELM1); /* Set Master clock MCLK to XT2CLK div 1 */
//Then set MCLK same as LFXT1CLK
//and SMCLK = XT2CLK/2
// BCSCTL2 = DIVS0+SELS+SELM0+SELM1;
/* Submain clock SMCLK is LFXT1CLK, XT2CLK or DCOCLK divided by 1, 2, 4 or
8. */
BCSCTL2 &= ~(DIVS1|DIVS0); /* Set Submain clock SMCLK divider to
div 1 */
BCSCTL2 |= (SELS); /* Set Submain clock SMCLK to XT2CLK */
}
>Hugh, thanks for your help, but I still seem to be having some
problems. Does there seem to be anything wrong with the code below?
Using the MSP430F149.
int gps_config(void)
{
unsigned int i;
WDTCTL = WDTPW + WDTHOLD; // turn watch dog timer off
BCSCTL1 = 0x04; // ACLK = LFXT1 = LF XTAL (32.768 kHz)
// This leaves XT2 on and able to be
// used for MCLK
do {
IFG1 &= ~OFIFG; // Clear OSCFault flag
for (i = 0xFF; i > 0; i--); // Time for flag to set
}
while ((IFG1 & OFIFG) == OFIFG); // OSCFault flag still set?
// UCTL1 = CHAR + PENA; // 8 bit data, odd parity enabled
UCTL1 = (CHAR + PENA) + SWRST; // 8 bit data, odd parity enabled
//UTCTL1 |= SSEL0 + SSEL1 + TXWAKE;
UTCTL1 = SSEL1; // UCLK = SMCLK
//URCTL1 = URXEIE;
UBR01 = 0x00; // 7.3728MHz 9600 baud - 768 or 0x0300
UBR11 = 0x03; //
UMCTL1 = 0x00; // no modulation because it divides evenly.
ME2 |= UTXE1 + URXE1; // Enable USART1 TXD/RXD
IE2 |= URXIE1 + UTXIE1; // Enable USART1 RX/TX interrupt
URCTL1 |= URXEIE; // UART 1 Receive Control - Allow error
characters to set interrupt
P3SEL |= 0xc0; // P3.6,7 = USART1 TXD/RXD
P3DIR |= 0x40; // P3.6 output direction
P4DIR |= 0x20; //P4.5 GPS enable output direction
P4OUT &= 0xDF; //p4.5 GPS enable low
UCTL1 &= ~SWRST; // Clear SWRST to enable uart
_EINT(); // Enable interrupts
P2DIR |= 0x80; //turn on yellow LED light, for testing purposes
P2OUT &= 0x7F;
//send messages configuring the GPS
xmit_buffer(&PortConfigString, PortConfigStringLength);
for(i = 0; i<1000; i++){} //pause to give it time to process
xmit_buffer(&NMEAConfigString, NMEAConfigStringLength);
//loop to wait for interrupt
dollarflag = 0;
while(dollarflag != 1){
}
P4DIR |= 0x80; //turn on red LED light, for testing purposes
P4OUT &= 0x7F;
return 1;
}
Reply by ●June 2, 20032003-06-02
Okay, I still can't seem to get it working. I tried to implement
some of your code, and here is what I have come up with. Is there
something else I need to be doing to set up SMCLK? Thanks so much
for all your help. I really appreciate it!
Blake
int gps_config(void)
{
unsigned int i;
WDTCTL = WDTPW + WDTHOLD; // turn watch dog timer off
IFG2 = 0; // Interrupt flag 2
IFG1 = 0; // Interrupt flag 1
BCSCTL1 = 0x04; // ACLK = LFXT1 = LF XTAL (32.768 kHz)
// This leaves XT2 on and able to be
// used for MCLK
/* do I need any of this stuff?
BCSCTL1 &= ~XT2OFF; // Enable XT2 crystal oscillator
BCSCTL1 &= ~XTS; // Enable low-frequency XT1 crystal oscillator
BCSCTL2 &= ~(DIVM1|DIVM0); //Set Master clock MCLK to XT2CLK div 1
BCSCTL2 &= ~(SELM0); //Set Master clock MCLK to XT2CLK div 1
BCSCTL2 |= (SELM1); //Set Master clock MCLK to XT2CLK div 1
*/
/* is this correct? */
BCSCTL2 &= ~(DIVS1|DIVS0); /* Set Submain clock SMCLK divider to
div 1 */
BCSCTL2 |= (SELS); /* Set Submain clock SMCLK to XT2CLK */
do {
IFG1 &= ~OFIFG; // Clear OSCFault flag
for (i = 0xFF; i > 0; i--); // Time for flag to set
}
while ((IFG1 & OFIFG) == OFIFG); // OSCFault flag still set?
// UCTL1 = CHAR + PENA; // 8 bit data, odd parity enabled
UCTL1 = (CHAR + PENA) + SWRST; // 8 bit data, odd parity enabled
//UTCTL1 |= SSEL0 + SSEL1 + TXWAKE;
UTCTL1 = SSEL1; // UCLK = SMCLK
//URCTL1 = URXEIE;
UBR01 = 0x00; // 7.3728MHz 9600 baud - 768 or 0x0300
UBR11 = 0x03; //
UMCTL1 = 0x00; // no modulation because it divides evenly.
ME2 |= UTXE1 + URXE1; // Enable USART1 TXD/RXD
IE2 |= URXIE1 + UTXIE1; // Enable USART1 RX/TX interrupt
URCTL1 |= URXEIE; // UART 1 Receive Control - Allow error
characters to set interrupt
P3SEL |= 0xc0; // P3.6,7 = USART1 TXD/RXD
P3DIR |= 0x40; // P3.6 output direction
P4DIR |= 0x20; //P4.5 GPS enable output direction
P4OUT &= 0xDF; //p4.5 GPS enable low
UCTL1 &= ~SWRST; // Clear SWRST to enable uart
_EINT(); // Enable interrupts
P2DIR |= 0x80; //turn on yellow LED light, for testing purposes
P2OUT &= 0x7F;
//send messages configured the GPS
xmit_buffer(&PortConfigString, PortConfigStringLength);
for(i = 0; i<1000; i++){}
xmit_buffer(&NMEAConfigString, NMEAConfigStringLength);
//loop to wait for interrupt
dollarflag = 0;
while(dollarflag != 1){
}
P4DIR |= 0x80; //turn on red LED light, for testing purposes
P4OUT &= 0x7F;
return 1;
}
--- In msp430@msp4..., Hugh Molesworth <nzbackpackers@y...>
wrote:
> Hi.
>
> Doesn't look like you're setting up SMCLK. Here's some old
MSP430F149 code
> I wrote which works fine, maybe you can see from
this what the
difference
> is. I'm just about to leave for the airport
so I hope that helps.
>
> Regards, Hugh
>
> void Start_Osc(void)
> {
> /*
> * DCO is CR typically ?
> *
> * LFXT1CLK is typically 32.768kHz watch crystal used for low
power.
> *
> * XT2CLK is typically 7.3728MHz crystal used for accurate high-
speed comms.
> *
> * There are 3 system clock lines: ACLK, MCLK & SMCLK.
> *
> * Auxilliary clock ACLK is buffered LFXT1CLK divided by 1, 2, 4
or 8.
> * Typically 32.768kHz watch crystal.
> *
> * Master clock MCLK is LFXT1CLK, XT2CLK or DCOCLK divided by 1,
2, 4 or 8.
> *
> * Submain clock SMCLK is LFXT1CLK, XT2CLK or DCOCLK divided by 1,
2, 4 or 8.
> */
>
> WDTCTL = WDTPW + WDTHOLD; // Stop watchdog timer
> IFG2 = 0; // Interrupt flag 2
> IFG1 = 0; // Interrupt flag 1
>
> /*
> * Enable LFXT1CLK (typically 32.768kHz watch crystal used for low
power)
> *
> * Enable XT2CLK (typically 7.3728MHz crystal used for accurate
high-speed
> comms)
> *
> */
> BCSCTL1 &= ~XT2OFF; // Enable XT2 crystal oscillator
> BCSCTL1 &= ~XTS; // Enable low-frequency XT1 crystal
oscillator
> do //wait in loop
until crystal is
stable
> {
> IFG1 &= ~OFIFG;
> } while (OFIFG&IFG1);
> Delay1();
> IFG1 &= ~OFIFG; // Reset osc. fault flag again
>
> /*
> * DCO is CR typically ? let's go max speed
> *
> */
> DCOCTL |= DCO0 | DCO1 | DCO2; // Max speed for DCO!
>
> /* Auxilliary clock ACLK is buffered LFXT1CLK divided by 1, 2, 4 or
8. */
> BCSCTL1 &= ~(DIVA0|DIVA1); // Set DCO
clock ACLK is
buffered
> LFXT1CLK divided by 1
>
> /* Master clock MCLK is LFXT1CLK, XT2CLK or DCOCLK divided by 1, 2,
4 or 8. */
> BCSCTL2 &= ~(DIVM1|DIVM0); /* Set Master
clock MCLK to XT2CLK
div 1 */
> BCSCTL2 &= ~(SELM0); /* Set Master clock
MCLK to XT2CLK div 1
*/
> BCSCTL2 |= (SELM1); /* Set Master clock
MCLK to XT2CLK div 1
*/
> //Then set MCLK
same as LFXT1CLK
> //and SMCLK = XT2CLK/2
> // BCSCTL2 = DIVS0+SELS+SELM0+SELM1;
>
>
> /* Submain clock SMCLK is LFXT1CLK, XT2CLK or DCOCLK divided by 1,
2, 4 or
> 8. */
> BCSCTL2 &= ~(DIVS1|DIVS0); /* Set Submain clock SMCLK
divider to
> div 1 */
> BCSCTL2 |= (SELS); /* Set Submain clock SMCLK to
XT2CLK */
> }
>
> >Hugh, thanks for your help, but I still seem to be having some
> problems. Does there seem to be anything wrong with the code below?
> Using the MSP430F149.
>
> int gps_config(void)
> {
> unsigned int i;
>
> WDTCTL = WDTPW + WDTHOLD; // turn watch dog timer off
>
>
> BCSCTL1 = 0x04; // ACLK = LFXT1 = LF XTAL (32.768 kHz)
> // This leaves XT2 on and able to be
> // used for MCLK
> do {
> IFG1 &= ~OFIFG; // Clear OSCFault flag
> for (i = 0xFF; i > 0; i--); // Time for flag to set
> }
> while ((IFG1 & OFIFG) == OFIFG); // OSCFault flag still set?
>
> // UCTL1 = CHAR + PENA; // 8 bit data, odd parity enabled
> UCTL1 = (CHAR + PENA) + SWRST; // 8 bit data, odd parity enabled
> //UTCTL1 |= SSEL0 + SSEL1 + TXWAKE;
> UTCTL1 = SSEL1; // UCLK = SMCLK
> //URCTL1 = URXEIE;
>
> UBR01 = 0x00; // 7.3728MHz 9600 baud - 768 or 0x0300
> UBR11 = 0x03; //
> UMCTL1 = 0x00; // no modulation because it divides evenly.
>
> ME2 |= UTXE1 + URXE1; // Enable USART1 TXD/RXD
> IE2 |= URXIE1 + UTXIE1; // Enable USART1 RX/TX interrupt
> URCTL1 |= URXEIE; // UART 1 Receive Control - Allow error
> characters to set interrupt
>
> P3SEL |= 0xc0; // P3.6,7 = USART1 TXD/RXD
> P3DIR |= 0x40; // P3.6 output direction
>
> P4DIR |= 0x20; //P4.5 GPS enable output direction
> P4OUT &= 0xDF; //p4.5 GPS enable low
>
> UCTL1 &= ~SWRST; // Clear SWRST to enable uart
>
> _EINT(); // Enable interrupts
>
> P2DIR |= 0x80; //turn on yellow LED light, for testing purposes
> P2OUT &= 0x7F;
>
> //send messages configuring the GPS
> xmit_buffer(&PortConfigString, PortConfigStringLength);
> for(i = 0; i<1000; i++){} //pause to give it time to process
> xmit_buffer(&NMEAConfigString, NMEAConfigStringLength);
>
> //loop to wait for interrupt
> dollarflag = 0;
> while(dollarflag != 1){
> }
>
> P4DIR |= 0x80; //turn on red LED light, for testing purposes
> P4OUT &= 0x7F;
>
> return 1;
> }
Reply by ●June 2, 20032003-06-02
You need these (which could be combined):
BCSCTL2 |= (SELM1); //Set Master clock MCLK to XT2CLK div 1 */
BCSCTL2 |= (SELS); /* Set Submain clock SMCLK to XT2CLK */
UTCTL1 = SSEL1; // UCLK = SMCLK
Most of the other stuff is already as you want it after a power-on reset.
I don't see anything obvious, maybe it's time to put a 'scope on
the rx pin
at the MSP430 and also pulse a pin from within the rx interrupt. Just to be
sure a valid signal is actually reaching the micro pin and that the
interrupt really isn't being triggered. I'm assuming your transmit
routine
is talking correctly to the GPS?
>Okay, I still can't seem to get it working. I tried to implement
some of your code, and here is what I have come up with. Is there
something else I need to be doing to set up SMCLK? Thanks so much
for all your help. I really appreciate it!
Blake
int gps_config(void)
{
unsigned int i;
WDTCTL = WDTPW + WDTHOLD; // turn watch dog timer off
IFG2 = 0; // Interrupt flag 2
IFG1 = 0; // Interrupt flag 1
BCSCTL1 = 0x04; // ACLK = LFXT1 = LF XTAL (32.768 kHz)
// This leaves XT2 on and able to be
// used for MCLK
/* do I need any of this stuff?
BCSCTL1 &= ~XT2OFF; // Enable XT2 crystal oscillator
BCSCTL1 &= ~XTS; // Enable low-frequency XT1 crystal oscillator
BCSCTL2 &= ~(DIVM1|DIVM0); //Set Master clock MCLK to XT2CLK div 1
BCSCTL2 &= ~(SELM0); //Set Master clock MCLK to XT2CLK div 1
BCSCTL2 |= (SELM1); //Set Master clock MCLK to XT2CLK div 1
*/
/* is this correct? */
BCSCTL2 &= ~(DIVS1|DIVS0); /* Set Submain clock SMCLK divider to
div 1 */
BCSCTL2 |= (SELS); /* Set Submain clock SMCLK to XT2CLK */
do {
IFG1 &= ~OFIFG; // Clear OSCFault flag
for (i = 0xFF; i > 0; i--); // Time for flag to set
}
while ((IFG1 & OFIFG) == OFIFG); // OSCFault flag still set?
// UCTL1 = CHAR + PENA; // 8 bit data, odd parity enabled
UCTL1 = (CHAR + PENA) + SWRST; // 8 bit data, odd parity enabled
//UTCTL1 |= SSEL0 + SSEL1 + TXWAKE;
UTCTL1 = SSEL1; // UCLK = SMCLK
//URCTL1 = URXEIE;
UBR01 = 0x00; // 7.3728MHz 9600 baud - 768 or 0x0300
UBR11 = 0x03; //
UMCTL1 = 0x00; // no modulation because it divides evenly.
ME2 |= UTXE1 + URXE1; // Enable USART1 TXD/RXD
IE2 |= URXIE1 + UTXIE1; // Enable USART1 RX/TX interrupt
URCTL1 |= URXEIE; // UART 1 Receive Control - Allow error
characters to set interrupt
P3SEL |= 0xc0; // P3.6,7 = USART1 TXD/RXD
P3DIR |= 0x40; // P3.6 output direction
P4DIR |= 0x20; //P4.5 GPS enable output direction
P4OUT &= 0xDF; //p4.5 GPS enable low
UCTL1 &= ~SWRST; // Clear SWRST to enable uart
_EINT(); // Enable interrupts
P2DIR |= 0x80; //turn on yellow LED light, for testing purposes
P2OUT &= 0x7F;
//send messages configured the GPS
xmit_buffer(&PortConfigString, PortConfigStringLength);
for(i = 0; i<1000; i++){}
xmit_buffer(&NMEAConfigString, NMEAConfigStringLength);
//loop to wait for interrupt
dollarflag = 0;
while(dollarflag != 1){
}
P4DIR |= 0x80; //turn on red LED light, for testing purposes
P4OUT &= 0x7F;
return 1;
}
--- In msp430@msp4..., Hugh Molesworth <nzbackpackers@y...>
wrote:
> Hi.
>
> Doesn't look like you're setting up SMCLK. Here's some old
MSP430F149 code
> I wrote which works fine, maybe you can see from this what the
difference
> is. I'm just about to leave for the airport so I hope that helps.
>
> Regards, Hugh
>
> void Start_Osc(void)
> {
> /*
> * DCO is CR typically ?
> *
> * LFXT1CLK is typically 32.768kHz watch crystal used for low
power.
> *
> * XT2CLK is typically 7.3728MHz crystal used for accurate high-
speed comms.
> *
> * There are 3 system clock lines: ACLK, MCLK & SMCLK.
> *
> * Auxilliary clock ACLK is buffered LFXT1CLK divided by 1, 2, 4
or 8.
> * Typically 32.768kHz watch crystal.
> *
> * Master clock MCLK is LFXT1CLK, XT2CLK or DCOCLK divided by 1,
2, 4 or 8.
> *
> * Submain clock SMCLK is LFXT1CLK, XT2CLK or DCOCLK divided by 1,
2, 4 or 8.
> */
>
> WDTCTL = WDTPW + WDTHOLD; // Stop watchdog timer
> IFG2 = 0; // Interrupt flag 2
> IFG1 = 0; // Interrupt flag 1
>
> /*
> * Enable LFXT1CLK (typically 32.768kHz watch crystal used for low
power)
> *
> * Enable XT2CLK (typically 7.3728MHz crystal used for accurate
high-speed
> comms)
> *
> */
> BCSCTL1 &= ~XT2OFF; // Enable XT2 crystal oscillator
> BCSCTL1 &= ~XTS; // Enable low-frequency XT1 crystal
oscillator
> do //wait in loop until crystal is
stable
> {
> IFG1 &= ~OFIFG;
> } while (OFIFG&IFG1);
> Delay1();
> IFG1 &= ~OFIFG; // Reset osc. fault flag again
>
> /*
> * DCO is CR typically ? let's go max speed
> *
> */
> DCOCTL |= DCO0 | DCO1 | DCO2; // Max speed for DCO!
>
> /* Auxilliary clock ACLK is buffered LFXT1CLK divided by 1, 2, 4 or
8. */
> BCSCTL1 &= ~(DIVA0|DIVA1); // Set DCO clock ACLK is
buffered
> LFXT1CLK divided by 1
>
> /* Master clock MCLK is LFXT1CLK, XT2CLK or DCOCLK divided by 1, 2,
4 or 8. */
> BCSCTL2 &= ~(DIVM1|DIVM0); /* Set Master clock MCLK to XT2CLK
div 1 */
> BCSCTL2 &= ~(SELM0); /* Set Master clock MCLK to XT2CLK div 1
*/
> BCSCTL2 |= (SELM1); /* Set Master clock MCLK to XT2CLK div 1
*/
> //Then set MCLK same as LFXT1CLK
> //and SMCLK = XT2CLK/2
> // BCSCTL2 = DIVS0+SELS+SELM0+SELM1;
>
>
> /* Submain clock SMCLK is LFXT1CLK, XT2CLK or DCOCLK divided by 1,
2, 4 or
> 8. */
> BCSCTL2 &= ~(DIVS1|DIVS0); /* Set Submain clock SMCLK
divider to
> div 1 */
> BCSCTL2 |= (SELS); /* Set Submain clock SMCLK to
XT2CLK */
> }
>
> >Hugh, thanks for your help, but I still seem to be having some
> problems. Does there seem to be anything wrong with the code below?
> Using the MSP430F149.
>
> int gps_config(void)
> {
> unsigned int i;
>
> WDTCTL = WDTPW + WDTHOLD; // turn watch dog timer off
>
>
> BCSCTL1 = 0x04; // ACLK = LFXT1 = LF XTAL (32.768 kHz)
> // This leaves XT2 on and able to be
> // used for MCLK
> do {
> IFG1 &= ~OFIFG; // Clear OSCFault flag
> for (i = 0xFF; i > 0; i--); // Time for flag to set
> }
> while ((IFG1 & OFIFG) == OFIFG); // OSCFault flag still set?
>
> // UCTL1 = CHAR + PENA; // 8 bit data, odd parity enabled
> UCTL1 = (CHAR + PENA) + SWRST; // 8 bit data, odd parity enabled
> //UTCTL1 |= SSEL0 + SSEL1 + TXWAKE;
> UTCTL1 = SSEL1; // UCLK = SMCLK
> //URCTL1 = URXEIE;
>
> UBR01 = 0x00; // 7.3728MHz 9600 baud - 768 or 0x0300
> UBR11 = 0x03; //
> UMCTL1 = 0x00; // no modulation because it divides evenly.
>
> ME2 |= UTXE1 + URXE1; // Enable USART1 TXD/RXD
> IE2 |= URXIE1 + UTXIE1; // Enable USART1 RX/TX interrupt
> URCTL1 |= URXEIE; // UART 1 Receive Control - Allow error
> characters to set interrupt
>
> P3SEL |= 0xc0; // P3.6,7 = USART1 TXD/RXD
> P3DIR |= 0x40; // P3.6 output direction
>
> P4DIR |= 0x20; //P4.5 GPS enable output direction
> P4OUT &= 0xDF; //p4.5 GPS enable low
>
> UCTL1 &= ~SWRST; // Clear SWRST to enable uart
>
> _EINT(); // Enable interrupts
>
> P2DIR |= 0x80; //turn on yellow LED light, for testing purposes
> P2OUT &= 0x7F;
>
> //send messages configuring the GPS
> xmit_buffer(&PortConfigString, PortConfigStringLength);
> for(i = 0; i<1000; i++){} //pause to give it time to process
> xmit_buffer(&NMEAConfigString, NMEAConfigStringLength);
>
> //loop to wait for interrupt
> dollarflag = 0;
> while(dollarflag != 1){
> }
>
> P4DIR |= 0x80; //turn on red LED light, for testing purposes
> P4OUT &= 0x7F;
>
> return 1;
> }
Reply by ●June 2, 20032003-06-02
Thanks Hugh. We'll try using the oscilloscope. I think it is communicating correctly with the GPS, but truthfully I don't really know for sure. I'll try working on it some more. Thanks! --- In msp430@msp4..., Hugh Molesworth <nzbackpackers@y...> wrote: > You need these (which could be combined): > > BCSCTL2 |= (SELM1); //Set Master clock MCLK to XT2CLK div 1 */ > BCSCTL2 |= (SELS); /* Set Submain clock SMCLK to XT2CLK */ > > UTCTL1 = SSEL1; // UCLK = SMCLK > > Most of the other stuff is already as you want it after a power-on reset. > > I don't see anything obvious, maybe it's time to put a 'scope on the rx pin > at the MSP430 and also pulse a pin from within the rx interrupt. Just to be > sure a valid signal is actually reaching the micro pin and that the > interrupt really isn't being triggered. I'm assuming your transmit routine > is talking correctly to the GPS? > > >Okay, I still can't seem to get it working. I tried to implement > some of your code, and here is what I have come up with. Is there > something else I need to be doing to set up SMCLK? Thanks so much > for all your help. I really appreciate it! > Blake > > int gps_config(void) > { > unsigned int i; > > WDTCTL = WDTPW + WDTHOLD; // turn watch dog timer off > IFG2 = 0; // Interrupt flag 2 > IFG1 = 0; // Interrupt flag 1 > > BCSCTL1 = 0x04; // ACLK = LFXT1 = LF XTAL (32.768 kHz) > // This leaves XT2 on and able to be > // used for MCLK > > /* do I need any of this stuff? > BCSCTL1 &= ~XT2OFF; // Enable XT2 crystal oscillator > BCSCTL1 &= ~XTS; // Enable low-frequency XT1 crystal oscillator > > BCSCTL2 &= ~(DIVM1|DIVM0); //Set Master clock MCLK to XT2CLK div 1 > BCSCTL2 &= ~(SELM0); //Set Master clock MCLK to XT2CLK div 1 > BCSCTL2 |= (SELM1); //Set Master clock MCLK to XT2CLK div 1 > */ > > /* is this correct? */ > BCSCTL2 &= ~(DIVS1|DIVS0); /* Set Submain clock SMCLK divider to > div 1 */ > BCSCTL2 |= (SELS); /* Set Submain clock SMCLK to XT2CLK */ > > do { > IFG1 &= ~OFIFG; // Clear OSCFault flag > for (i = 0xFF; i > 0; i--); // Time for flag to set > } > while ((IFG1 & OFIFG) == OFIFG); // OSCFault flag still set? > > // UCTL1 = CHAR + PENA; // 8 bit data, odd parity enabled > UCTL1 = (CHAR + PENA) + SWRST; // 8 bit data, odd parity enabled > //UTCTL1 |= SSEL0 + SSEL1 + TXWAKE; > UTCTL1 = SSEL1; // UCLK = SMCLK > //URCTL1 = URXEIE; > > UBR01 = 0x00; // 7.3728MHz 9600 baud - 768 or 0x0300 > UBR11 = 0x03; // > UMCTL1 = 0x00; // no modulation because it divides evenly. > > ME2 |= UTXE1 + URXE1; // Enable USART1 TXD/RXD > IE2 |= URXIE1 + UTXIE1; // Enable USART1 RX/TX interrupt > URCTL1 |= URXEIE; // UART 1 Receive Control - Allow error > characters to set interrupt > > P3SEL |= 0xc0; // P3.6,7 = USART1 TXD/RXD > P3DIR |= 0x40; // P3.6 output direction > > P4DIR |= 0x20; //P4.5 GPS enable output direction > P4OUT &= 0xDF; //p4.5 GPS enable low > > UCTL1 &= ~SWRST; // Clear SWRST to enable uart > > _EINT(); // Enable interrupts > > P2DIR |= 0x80; //turn on yellow LED light, for testing purposes > P2OUT &= 0x7F; > > //send messages configured the GPS > xmit_buffer(&PortConfigString, PortConfigStringLength); > for(i = 0; i<1000; i++){} > xmit_buffer(&NMEAConfigString, NMEAConfigStringLength); > > //loop to wait for interrupt > dollarflag = 0; > while(dollarflag != 1){ > } > > P4DIR |= 0x80; //turn on red LED light, for testing purposes > P4OUT &= 0x7F; > > return 1; > } > > --- In msp430@msp4..., Hugh Molesworth <nzbackpackers@y...> > wrote: > > Hi. > > > > Doesn't look like you're setting up SMCLK. Here's some old > MSP430F149 code > > I wrote which works fine, maybe you can see from this what the > difference > > is. I'm just about to leave for the airport so I hope that helps. > > > > Regards, Hugh > > > > void Start_Osc(void) > > { > > /* > > * DCO is CR typically ? > > * > > * LFXT1CLK is typically 32.768kHz watch crystal used for low > power. > > * > > * XT2CLK is typically 7.3728MHz crystal used for accurate high- > speed comms. > > * > > * There are 3 system clock lines: ACLK, MCLK & SMCLK. > > * > > * Auxilliary clock ACLK is buffered LFXT1CLK divided by 1, 2, 4 > or 8. > > * Typically 32.768kHz watch crystal. > > * > > * Master clock MCLK is LFXT1CLK, XT2CLK or DCOCLK divided by 1, > 2, 4 or 8. > > * > > * Submain clock SMCLK is LFXT1CLK, XT2CLK or DCOCLK divided by 1, > 2, 4 or 8. > > */ > > > > WDTCTL = WDTPW + WDTHOLD; // Stop watchdog timer > > IFG2 = 0; // Interrupt flag 2 > > IFG1 = 0; // Interrupt flag 1 > > > > /* > > * Enable LFXT1CLK (typically 32.768kHz watch crystal used for low > power) > > * > > * Enable XT2CLK (typically 7.3728MHz crystal used for accurate > high-speed > > comms) > > * > > */ > > BCSCTL1 &= ~XT2OFF; // Enable XT2 crystal oscillator > > BCSCTL1 &= ~XTS; // Enable low-frequency XT1 crystal > oscillator > > do //wait in loop until crystal is > stable > > { > > IFG1 &= ~OFIFG; > > } while (OFIFG&IFG1); > > Delay1(); > > IFG1 &= ~OFIFG; // Reset osc. fault flag again > > > > /* > > * DCO is CR typically ? let's go max speed > > * > > */ > > DCOCTL |= DCO0 | DCO1 | DCO2; // Max speed for DCO! > > > > /* Auxilliary clock ACLK is buffered LFXT1CLK divided by 1, 2, 4 or > 8. */ > > BCSCTL1 &= ~(DIVA0|DIVA1); // Set DCO clock ACLK is > buffered > > LFXT1CLK divided by 1 > > > > /* Master clock MCLK is LFXT1CLK, XT2CLK or DCOCLK divided by 1, 2, > 4 or 8. */ > > BCSCTL2 &= ~(DIVM1|DIVM0); /* Set Master clock MCLK to XT2CLK > div 1 */ > > BCSCTL2 &= ~(SELM0); /* Set Master clock MCLK to XT2CLK div 1 > */ > > BCSCTL2 |= (SELM1); /* Set Master clock MCLK to XT2CLK div 1 > */ > > //Then set MCLK same as LFXT1CLK > > //and SMCLK = XT2CLK/2 > > // BCSCTL2 = DIVS0+SELS+SELM0+SELM1; > > > > > > /* Submain clock SMCLK is LFXT1CLK, XT2CLK or DCOCLK divided by 1, > 2, 4 or > > 8. */ > > BCSCTL2 &= ~(DIVS1|DIVS0); /* Set Submain clock SMCLK > divider to > > div 1 */ > > BCSCTL2 |= (SELS); /* Set Submain clock SMCLK to > XT2CLK */ > > } > > > > >Hugh, thanks for your help, but I still seem to be having some > > problems. Does there seem to be anything wrong with the code below? > > Using the MSP430F149. > > > > int gps_config(void) > > { > > unsigned int i; > > > > WDTCTL = WDTPW + WDTHOLD; // turn watch dog timer off > > > > > > BCSCTL1 = 0x04; // ACLK = LFXT1 = LF XTAL (32.768 kHz) > > // This leaves XT2 on and able to be > > // used for MCLK > > do { > > IFG1 &= ~OFIFG; // Clear OSCFault flag > > for (i = 0xFF; i > 0; i--); // Time for flag to set > > } > > while ((IFG1 & OFIFG) == OFIFG); // OSCFault flag still set? > > > > // UCTL1 = CHAR + PENA; // 8 bit data, odd parity enabled > > UCTL1 = (CHAR + PENA) + SWRST; // 8 bit data, odd parity enabled > > //UTCTL1 |= SSEL0 + SSEL1 + TXWAKE; > > UTCTL1 = SSEL1; // UCLK = SMCLK > > //URCTL1 = URXEIE; > > > > UBR01 = 0x00; // 7.3728MHz 9600 baud - 768 or 0x0300 > > UBR11 = 0x03; // > > UMCTL1 = 0x00; // no modulation because it divides evenly. > > > > ME2 |= UTXE1 + URXE1; // Enable USART1 TXD/RXD > > IE2 |= URXIE1 + UTXIE1; // Enable USART1 RX/TX interrupt > > URCTL1 |= URXEIE; // UART 1 Receive Control - Allow error > > characters to set interrupt > > > > P3SEL |= 0xc0; // P3.6,7 = USART1 TXD/RXD > > P3DIR |= 0x40; // P3.6 output direction > > > > P4DIR |= 0x20; //P4.5 GPS enable output direction > > P4OUT &= 0xDF; //p4.5 GPS enable low > > > > UCTL1 &= ~SWRST; // Clear SWRST to enable uart > > > > _EINT(); // Enable interrupts > > > > P2DIR |= 0x80; //turn on yellow LED light, for testing purposes > > P2OUT &= 0x7F; > > > > //send messages configuring the GPS > > xmit_buffer(&PortConfigString, PortConfigStringLength); > > for(i = 0; i<1000; i++){} //pause to give it time to process > > xmit_buffer(&NMEAConfigString, NMEAConfigStringLength); > > > > //loop to wait for interrupt > > dollarflag = 0; > > while(dollarflag != 1){ > > } > > > > P4DIR |= 0x80; //turn on red LED light, for testing purposes > > P4OUT &= 0x7F; > > > > return 1; > > }
Reply by ●June 3, 20032003-06-03
I don't have the documentation with me now but I'm quite sure
oscilator
checking doesn't work with LF crystals. (You anre going to wait forever for
OFIFG).
Besides, take into account that the manual says that if you use such a
crystal for MCLK you are going to have "increased current
consumption".
One more: I tried to use a 32K Xtal for 9600 baud and the result were not
good. The MSP could transmit OK but once in a while it received a corrupted
byte.
Regards,
Claudio
> -----Original Message-----
> From: Blake [SMTP:blake@blak...]
> Sent: Monday, June 02, 2003 6:16 PM
> To: msp430@msp4...
> Subject: [msp430] Re: setting up uart communication for 9600 baud
> rate
>
> Thanks Hugh. We'll try using the oscilloscope. I think it is
> communicating correctly with the GPS, but truthfully I don't really
> know for sure. I'll try working on it some more. Thanks!
>
> --- In msp430@msp4..., Hugh Molesworth <nzbackpackers@y...>
> wrote:
> > You need these (which could be combined):
> >
> > BCSCTL2 |= (SELM1); //Set Master clock MCLK to XT2CLK div 1 */
> > BCSCTL2 |= (SELS); /* Set Submain clock SMCLK to XT2CLK */
> >
> > UTCTL1 = SSEL1; // UCLK = SMCLK
> >
> > Most of the other stuff is already as you want it after a power-on
> reset.
> >
> > I don't see anything obvious, maybe it's time to put a
'scope on
> the rx pin
> > at the MSP430 and also pulse a pin from within the rx interrupt.
> Just to be
> > sure a valid signal is actually reaching the micro pin and that the
> > interrupt really isn't being triggered. I'm assuming your
transmit
> routine
> > is talking correctly to the GPS?
> >
> > >Okay, I still can't seem to get it working. I tried to
implement
> > some of your code, and here is what I have come up with. Is there
> > something else I need to be doing to set up SMCLK? Thanks so much
> > for all your help. I really appreciate it!
> > Blake
> >
> > int gps_config(void)
> > {
> > unsigned int i;
> >
> > WDTCTL = WDTPW + WDTHOLD; // turn watch dog timer off
> > IFG2 = 0; // Interrupt flag 2
> > IFG1 = 0; // Interrupt flag 1
> >
> > BCSCTL1 = 0x04; // ACLK = LFXT1 = LF XTAL (32.768 kHz)
> > // This leaves XT2 on and able to be
> > // used for MCLK
> >
> > /* do I need any of this stuff?
> > BCSCTL1 &= ~XT2OFF; // Enable XT2 crystal oscillator
> > BCSCTL1 &= ~XTS; // Enable low-frequency XT1 crystal oscillator
> >
> > BCSCTL2 &= ~(DIVM1|DIVM0); //Set Master clock MCLK to XT2CLK div 1
> > BCSCTL2 &= ~(SELM0); //Set Master clock MCLK to XT2CLK div 1
> > BCSCTL2 |= (SELM1); //Set Master clock MCLK to XT2CLK div 1
> > */
> >
> > /* is this correct? */
> > BCSCTL2 &= ~(DIVS1|DIVS0); /* Set Submain clock SMCLK divider to
> > div 1 */
> > BCSCTL2 |= (SELS); /* Set Submain clock SMCLK to XT2CLK */
> >
> > do {
> > IFG1 &= ~OFIFG; // Clear OSCFault flag
> > for (i = 0xFF; i > 0; i--); // Time for flag to set
> > }
> > while ((IFG1 & OFIFG) == OFIFG); // OSCFault flag still set?
> >
> > // UCTL1 = CHAR + PENA; // 8 bit data, odd parity enabled
> > UCTL1 = (CHAR + PENA) + SWRST; // 8 bit data, odd parity enabled
> > //UTCTL1 |= SSEL0 + SSEL1 + TXWAKE;
> > UTCTL1 = SSEL1; // UCLK = SMCLK
> > //URCTL1 = URXEIE;
> >
> > UBR01 = 0x00; // 7.3728MHz 9600 baud - 768 or 0x0300
> > UBR11 = 0x03; //
> > UMCTL1 = 0x00; // no modulation because it divides evenly.
> >
> > ME2 |= UTXE1 + URXE1; // Enable USART1 TXD/RXD
> > IE2 |= URXIE1 + UTXIE1; // Enable USART1 RX/TX interrupt
> > URCTL1 |= URXEIE; // UART 1 Receive Control - Allow error
> > characters to set interrupt
> >
> > P3SEL |= 0xc0; // P3.6,7 = USART1 TXD/RXD
> > P3DIR |= 0x40; // P3.6 output direction
> >
> > P4DIR |= 0x20; //P4.5 GPS enable output direction
> > P4OUT &= 0xDF; //p4.5 GPS enable low
> >
> > UCTL1 &= ~SWRST; // Clear SWRST to enable uart
> >
> > _EINT(); // Enable interrupts
> >
> > P2DIR |= 0x80; //turn on yellow LED light, for testing purposes
> > P2OUT &= 0x7F;
> >
> > //send messages configured the GPS
> > xmit_buffer(&PortConfigString, PortConfigStringLength);
> > for(i = 0; i<1000; i++){}
> > xmit_buffer(&NMEAConfigString, NMEAConfigStringLength);
> >
> > //loop to wait for interrupt
> > dollarflag = 0;
> > while(dollarflag != 1){
> > }
> >
> > P4DIR |= 0x80; //turn on red LED light, for testing purposes
> > P4OUT &= 0x7F;
> >
> > return 1;
> > }
> >
> > --- In msp430@msp4..., Hugh Molesworth <nzbackpackers@y...>
> > wrote:
> > > Hi.
> > >
> > > Doesn't look like you're setting up SMCLK. Here's
some old
> > MSP430F149 code
> > > I wrote which works fine, maybe you can see from this what the
> > difference
> > > is. I'm just about to leave for the airport so I hope that
helps.
> > >
> > > Regards, Hugh
> > >
> > > void Start_Osc(void)
> > > {
> > > /*
> > > * DCO is CR typically ?
> > > *
> > > * LFXT1CLK is typically 32.768kHz watch crystal used for low
> > power.
> > > *
> > > * XT2CLK is typically 7.3728MHz crystal used for accurate high-
> > speed comms.
> > > *
> > > * There are 3 system clock lines: ACLK, MCLK & SMCLK.
> > > *
> > > * Auxilliary clock ACLK is buffered LFXT1CLK divided by 1, 2, 4
> > or 8.
> > > * Typically 32.768kHz watch crystal.
> > > *
> > > * Master clock MCLK is LFXT1CLK, XT2CLK or DCOCLK divided by 1,
> > 2, 4 or 8.
> > > *
> > > * Submain clock SMCLK is LFXT1CLK, XT2CLK or DCOCLK divided by
1,
> > 2, 4 or 8.
> > > */
> > >
> > > WDTCTL = WDTPW + WDTHOLD; // Stop watchdog timer
> > > IFG2 = 0; // Interrupt flag 2
> > > IFG1 = 0; // Interrupt flag 1
> > >
> > > /*
> > > * Enable LFXT1CLK (typically 32.768kHz watch crystal used for
low
> > power)
> > > *
> > > * Enable XT2CLK (typically 7.3728MHz crystal used for accurate
> > high-speed
> > > comms)
> > > *
> > > */
> > > BCSCTL1 &= ~XT2OFF; // Enable XT2 crystal oscillator
> > > BCSCTL1 &= ~XTS; // Enable low-frequency XT1 crystal
> > oscillator
> > > do //wait in loop until crystal is
> > stable
> > > {
> > > IFG1 &= ~OFIFG;
> > > } while (OFIFG&IFG1);
> > > Delay1();
> > > IFG1 &= ~OFIFG; // Reset osc. fault flag again
> > >
> > > /*
> > > * DCO is CR typically ? let's go max speed
> > > *
> > > */
> > > DCOCTL |= DCO0 | DCO1 | DCO2; // Max speed for DCO!
> > >
> > > /* Auxilliary clock ACLK is buffered LFXT1CLK divided by 1, 2, 4
> or
> > 8. */
> > > BCSCTL1 &= ~(DIVA0|DIVA1); // Set DCO clock ACLK is
> > buffered
> > > LFXT1CLK divided by 1
> > >
> > > /* Master clock MCLK is LFXT1CLK, XT2CLK or DCOCLK divided by 1,
> 2,
> > 4 or 8. */
> > > BCSCTL2 &= ~(DIVM1|DIVM0); /* Set Master clock MCLK to
XT2CLK
> > div 1 */
> > > BCSCTL2 &= ~(SELM0); /* Set Master clock MCLK to XT2CLK div
1
> > */
> > > BCSCTL2 |= (SELM1); /* Set Master clock MCLK to XT2CLK div 1
> > */
> > > //Then set MCLK same as LFXT1CLK
> > > //and SMCLK = XT2CLK/2
> > > // BCSCTL2 = DIVS0+SELS+SELM0+SELM1;
> > >
> > >
> > > /* Submain clock SMCLK is LFXT1CLK, XT2CLK or DCOCLK divided by
> 1,
> > 2, 4 or
> > > 8. */
> > > BCSCTL2 &= ~(DIVS1|DIVS0); /* Set Submain clock SMCLK
> > divider to
> > > div 1 */
> > > BCSCTL2 |= (SELS); /* Set Submain clock SMCLK to
> > XT2CLK */
> > > }
> > >
> > > >Hugh, thanks for your help, but I still seem to be having
some
> > > problems. Does there seem to be anything wrong with the code
> below?
> > > Using the MSP430F149.
> > >
> > > int gps_config(void)
> > > {
> > > unsigned int i;
> > >
> > > WDTCTL = WDTPW + WDTHOLD; // turn watch dog timer off
> > >
> > >
> > > BCSCTL1 = 0x04; // ACLK = LFXT1 = LF XTAL (32.768 kHz)
> > > // This leaves XT2 on and able to be
> > > // used for MCLK
> > > do {
> > > IFG1 &= ~OFIFG; // Clear OSCFault flag
> > > for (i = 0xFF; i > 0; i--); // Time for flag to set
> > > }
> > > while ((IFG1 & OFIFG) == OFIFG); // OSCFault flag still set?
> > >
> > > // UCTL1 = CHAR + PENA; // 8 bit data, odd parity enabled
> > > UCTL1 = (CHAR + PENA) + SWRST; // 8 bit data, odd parity enabled
> > > //UTCTL1 |= SSEL0 + SSEL1 + TXWAKE;
> > > UTCTL1 = SSEL1; // UCLK = SMCLK
> > > //URCTL1 = URXEIE;
> > >
> > > UBR01 = 0x00; // 7.3728MHz 9600 baud - 768 or 0x0300
> > > UBR11 = 0x03; //
> > > UMCTL1 = 0x00; // no modulation because it divides evenly.
> > >
> > > ME2 |= UTXE1 + URXE1; // Enable USART1 TXD/RXD
> > > IE2 |= URXIE1 + UTXIE1; // Enable USART1 RX/TX interrupt
> > > URCTL1 |= URXEIE; // UART 1 Receive Control - Allow error
> > > characters to set interrupt
> > >
> > > P3SEL |= 0xc0; // P3.6,7 = USART1 TXD/RXD
> > > P3DIR |= 0x40; // P3.6 output direction
> > >
> > > P4DIR |= 0x20; //P4.5 GPS enable output direction
> > > P4OUT &= 0xDF; //p4.5 GPS enable low
> > >
> > > UCTL1 &= ~SWRST; // Clear SWRST to enable uart
> > >
> > > _EINT(); // Enable interrupts
> > >
> > > P2DIR |= 0x80; //turn on yellow LED light, for testing purposes
> > > P2OUT &= 0x7F;
> > >
> > > //send messages configuring the GPS
> > > xmit_buffer(&PortConfigString, PortConfigStringLength);
> > > for(i = 0; i<1000; i++){} //pause to give it time to
process
> > > xmit_buffer(&NMEAConfigString, NMEAConfigStringLength);
> > >
> > > //loop to wait for interrupt
> > > dollarflag = 0;
> > > while(dollarflag != 1){
> > > }
> > >
> > > P4DIR |= 0x80; //turn on red LED light, for testing purposes
> > > P4OUT &= 0x7F;
> > >
> > > return 1;
> > > }
>
>
>
> .
>
>
>
> ">http://docs.yahoo.com/info/terms/
>
Reply by ●June 3, 20032003-06-03
We finally got it to work. The problem was that we were trying to enable the interrups before we cleared the SWRST. When I moved the interrupt enable line below the SWRST line, it started to work. Thanks for all your help! --- In msp430@msp4..., "Blake" <blake@e...> wrote: > Thanks Hugh. We'll try using the oscilloscope. I think it is > communicating correctly with the GPS, but truthfully I don't really > know for sure. I'll try working on it some more. Thanks! > > --- In msp430@msp4..., Hugh Molesworth <nzbackpackers@y...> > wrote: > > You need these (which could be combined): > > > > BCSCTL2 |= (SELM1); //Set Master clock MCLK to XT2CLK div 1 */ > > BCSCTL2 |= (SELS); /* Set Submain clock SMCLK to XT2CLK */ > > > > UTCTL1 = SSEL1; // UCLK = SMCLK > > > > Most of the other stuff is already as you want it after a power- on > reset. > > > > I don't see anything obvious, maybe it's time to put a 'scope on > the rx pin > > at the MSP430 and also pulse a pin from within the rx interrupt. > Just to be > > sure a valid signal is actually reaching the micro pin and that the > > interrupt really isn't being triggered. I'm assuming your transmit > routine > > is talking correctly to the GPS? > > > > >Okay, I still can't seem to get it working. I tried to implement > > some of your code, and here is what I have come up with. Is there > > something else I need to be doing to set up SMCLK? Thanks so much > > for all your help. I really appreciate it! > > Blake > > > > int gps_config(void) > > { > > unsigned int i; > > > > WDTCTL = WDTPW + WDTHOLD; // turn watch dog timer off > > IFG2 = 0; // Interrupt flag 2 > > IFG1 = 0; // Interrupt flag 1 > > > > BCSCTL1 = 0x04; // ACLK = LFXT1 = LF XTAL (32.768 kHz) > > // This leaves XT2 on and able to be > > // used for MCLK > > > > /* do I need any of this stuff? > > BCSCTL1 &= ~XT2OFF; // Enable XT2 crystal oscillator > > BCSCTL1 &= ~XTS; // Enable low-frequency XT1 crystal oscillator > > > > BCSCTL2 &= ~(DIVM1|DIVM0); //Set Master clock MCLK to XT2CLK div 1 > > BCSCTL2 &= ~(SELM0); //Set Master clock MCLK to XT2CLK div 1 > > BCSCTL2 |= (SELM1); //Set Master clock MCLK to XT2CLK div 1 > > */ > > > > /* is this correct? */ > > BCSCTL2 &= ~(DIVS1|DIVS0); /* Set Submain clock SMCLK divider to > > div 1 */ > > BCSCTL2 |= (SELS); /* Set Submain clock SMCLK to XT2CLK */ > > > > do { > > IFG1 &= ~OFIFG; // Clear OSCFault flag > > for (i = 0xFF; i > 0; i--); // Time for flag to set > > } > > while ((IFG1 & OFIFG) == OFIFG); // OSCFault flag still set? > > > > // UCTL1 = CHAR + PENA; // 8 bit data, odd parity enabled > > UCTL1 = (CHAR + PENA) + SWRST; // 8 bit data, odd parity enabled > > //UTCTL1 |= SSEL0 + SSEL1 + TXWAKE; > > UTCTL1 = SSEL1; // UCLK = SMCLK > > //URCTL1 = URXEIE; > > > > UBR01 = 0x00; // 7.3728MHz 9600 baud - 768 or 0x0300 > > UBR11 = 0x03; // > > UMCTL1 = 0x00; // no modulation because it divides evenly. > > > > ME2 |= UTXE1 + URXE1; // Enable USART1 TXD/RXD > > IE2 |= URXIE1 + UTXIE1; // Enable USART1 RX/TX interrupt > > URCTL1 |= URXEIE; // UART 1 Receive Control - Allow error > > characters to set interrupt > > > > P3SEL |= 0xc0; // P3.6,7 = USART1 TXD/RXD > > P3DIR |= 0x40; // P3.6 output direction > > > > P4DIR |= 0x20; //P4.5 GPS enable output direction > > P4OUT &= 0xDF; //p4.5 GPS enable low > > > > UCTL1 &= ~SWRST; // Clear SWRST to enable uart > > > > _EINT(); // Enable interrupts > > > > P2DIR |= 0x80; //turn on yellow LED light, for testing purposes > > P2OUT &= 0x7F; > > > > //send messages configured the GPS > > xmit_buffer(&PortConfigString, PortConfigStringLength); > > for(i = 0; i<1000; i++){} > > xmit_buffer(&NMEAConfigString, NMEAConfigStringLength); > > > > //loop to wait for interrupt > > dollarflag = 0; > > while(dollarflag != 1){ > > } > > > > P4DIR |= 0x80; //turn on red LED light, for testing purposes > > P4OUT &= 0x7F; > > > > return 1; > > } > > > > --- In msp430@msp4..., Hugh Molesworth <nzbackpackers@y...> > > wrote: > > > Hi. > > > > > > Doesn't look like you're setting up SMCLK. Here's some old > > MSP430F149 code > > > I wrote which works fine, maybe you can see from this what the > > difference > > > is. I'm just about to leave for the airport so I hope that helps. > > > > > > Regards, Hugh > > > > > > void Start_Osc(void) > > > { > > > /* > > > * DCO is CR typically ? > > > * > > > * LFXT1CLK is typically 32.768kHz watch crystal used for low > > power. > > > * > > > * XT2CLK is typically 7.3728MHz crystal used for accurate high- > > speed comms. > > > * > > > * There are 3 system clock lines: ACLK, MCLK & SMCLK. > > > * > > > * Auxilliary clock ACLK is buffered LFXT1CLK divided by 1, 2, 4 > > or 8. > > > * Typically 32.768kHz watch crystal. > > > * > > > * Master clock MCLK is LFXT1CLK, XT2CLK or DCOCLK divided by 1, > > 2, 4 or 8. > > > * > > > * Submain clock SMCLK is LFXT1CLK, XT2CLK or DCOCLK divided by 1, > > 2, 4 or 8. > > > */ > > > > > > WDTCTL = WDTPW + WDTHOLD; // Stop watchdog timer > > > IFG2 = 0; // Interrupt flag 2 > > > IFG1 = 0; // Interrupt flag 1 > > > > > > /* > > > * Enable LFXT1CLK (typically 32.768kHz watch crystal used for low > > power) > > > * > > > * Enable XT2CLK (typically 7.3728MHz crystal used for accurate > > high-speed > > > comms) > > > * > > > */ > > > BCSCTL1 &= ~XT2OFF; // Enable XT2 crystal oscillator > > > BCSCTL1 &= ~XTS; // Enable low-frequency XT1 crystal > > oscillator > > > do //wait in loop until crystal is > > stable > > > { > > > IFG1 &= ~OFIFG; > > > } while (OFIFG&IFG1); > > > Delay1(); > > > IFG1 &= ~OFIFG; // Reset osc. fault flag again > > > > > > /* > > > * DCO is CR typically ? let's go max speed > > > * > > > */ > > > DCOCTL |= DCO0 | DCO1 | DCO2; // Max speed for DCO! > > > > > > /* Auxilliary clock ACLK is buffered LFXT1CLK divided by 1, 2, 4 > or > > 8. */ > > > BCSCTL1 &= ~(DIVA0|DIVA1); // Set DCO clock ACLK is > > buffered > > > LFXT1CLK divided by 1 > > > > > > /* Master clock MCLK is LFXT1CLK, XT2CLK or DCOCLK divided by 1, > 2, > > 4 or 8. */ > > > BCSCTL2 &= ~(DIVM1|DIVM0); /* Set Master clock MCLK to XT2CLK > > div 1 */ > > > BCSCTL2 &= ~(SELM0); /* Set Master clock MCLK to XT2CLK div 1 > > */ > > > BCSCTL2 |= (SELM1); /* Set Master clock MCLK to XT2CLK div 1 > > */ > > > //Then set MCLK same as LFXT1CLK > > > //and SMCLK = XT2CLK/2 > > > // BCSCTL2 = DIVS0+SELS+SELM0+SELM1; > > > > > > > > > /* Submain clock SMCLK is LFXT1CLK, XT2CLK or DCOCLK divided by > 1, > > 2, 4 or > > > 8. */ > > > BCSCTL2 &= ~(DIVS1|DIVS0); /* Set Submain clock SMCLK > > divider to > > > div 1 */ > > > BCSCTL2 |= (SELS); /* Set Submain clock SMCLK to > > XT2CLK */ > > > } > > > > > > >Hugh, thanks for your help, but I still seem to be having some > > > problems. Does there seem to be anything wrong with the code > below? > > > Using the MSP430F149. > > > > > > int gps_config(void) > > > { > > > unsigned int i; > > > > > > WDTCTL = WDTPW + WDTHOLD; // turn watch dog timer off > > > > > > > > > BCSCTL1 = 0x04; // ACLK = LFXT1 = LF XTAL (32.768 kHz) > > > // This leaves XT2 on and able to be > > > // used for MCLK > > > do { > > > IFG1 &= ~OFIFG; // Clear OSCFault flag > > > for (i = 0xFF; i > 0; i--); // Time for flag to set > > > } > > > while ((IFG1 & OFIFG) == OFIFG); // OSCFault flag still set? > > > > > > // UCTL1 = CHAR + PENA; // 8 bit data, odd parity enabled > > > UCTL1 = (CHAR + PENA) + SWRST; // 8 bit data, odd parity enabled > > > //UTCTL1 |= SSEL0 + SSEL1 + TXWAKE; > > > UTCTL1 = SSEL1; // UCLK = SMCLK > > > //URCTL1 = URXEIE; > > > > > > UBR01 = 0x00; // 7.3728MHz 9600 baud - 768 or 0x0300 > > > UBR11 = 0x03; // > > > UMCTL1 = 0x00; // no modulation because it divides evenly. > > > > > > ME2 |= UTXE1 + URXE1; // Enable USART1 TXD/RXD > > > IE2 |= URXIE1 + UTXIE1; // Enable USART1 RX/TX interrupt > > > URCTL1 |= URXEIE; // UART 1 Receive Control - Allow error > > > characters to set interrupt > > > > > > P3SEL |= 0xc0; // P3.6,7 = USART1 TXD/RXD > > > P3DIR |= 0x40; // P3.6 output direction > > > > > > P4DIR |= 0x20; //P4.5 GPS enable output direction > > > P4OUT &= 0xDF; //p4.5 GPS enable low > > > > > > UCTL1 &= ~SWRST; // Clear SWRST to enable uart > > > > > > _EINT(); // Enable interrupts > > > > > > P2DIR |= 0x80; //turn on yellow LED light, for testing purposes > > > P2OUT &= 0x7F; > > > > > > //send messages configuring the GPS > > > xmit_buffer(&PortConfigString, PortConfigStringLength); > > > for(i = 0; i<1000; i++){} //pause to give it time to process > > > xmit_buffer(&NMEAConfigString, NMEAConfigStringLength); > > > > > > //loop to wait for interrupt > > > dollarflag = 0; > > > while(dollarflag != 1){ > > > } > > > > > > P4DIR |= 0x80; //turn on red LED light, for testing purposes > > > P4OUT &= 0x7F; > > > > > > return 1; > > > }
