John,
I agree with Kip when he says:
>You may be better off having multiple 25LC320 and
selecting the one you
>want externally.
In that way, there would not be firmware delays to worry about as you will
have with any micro-controller. I would bet most SPI slaves are NOT
micro-controllers but rather just logic (maybe programmable) that can
operate at very high speed.
I once used an MSP430F169 to implement an SPI slave device. To be a good
SPI slave without a lot of timing problems, you will have to use some DMA
device and keep the clock rates low. On the 'F169, I used Port 1 to
receive
the slave enable signal from the master as an interrupt. That interrupt
would set up the DMA system. Then I wrote code to have a double buffer
where one buffer could be updated while the other was available for the
master.
In my application, all the data was in one block and it was all or nothing;
there was no ability to pick which data to return. But in your case of
wanting to get to random locations, it would be difficult to arrange things
with an SPI control byte and clock edges coming in at 1 Mb/s rates. In my
slave, I also could restrict the master on the clock rate used, and went
only up to 100 Kb/s or so.
Lou
_________________________________________________________________
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MSP430 to emulate a SPI EEPROM
Started by ●December 19, 2006
Reply by ●December 20, 20062006-12-20
Reply by ●December 20, 20062006-12-20
Looks like emulating a 25LC320 with a micro is not practical in
general. But it may still be possible under special circumstances.
For example, if the master always read the bytes in a certain order,
the slave can anticipate what to send without waiting for the address
of the byte.
Another example is, if the master reads a block of bytes with some
kind of error checking. In this case, the slave could introduce
errors to force the master to re-read the block with the same
address. This would slow down the process, but acceptable for some
applications.
--- In m..., "Lou C" wrote:
>
> John,
>
> I agree with Kip when he says:
>
> >You may be better off having multiple 25LC320 and selecting the
one you
> >want externally.
>
> In that way, there would not be firmware delays to worry about as
you will
> have with any micro-controller. I would bet most SPI slaves are
NOT
> micro-controllers but rather just logic (maybe programmable) that
can
> operate at very high speed.
>
> I once used an MSP430F169 to implement an SPI slave device. To be
a good
> SPI slave without a lot of timing problems, you will have to use
some DMA
> device and keep the clock rates low. On the 'F169, I used Port 1
to receive
> the slave enable signal from the master as an interrupt. That
interrupt
> would set up the DMA system. Then I wrote code to have a double
buffer
> where one buffer could be updated while the other was available for
the
> master.
>
> In my application, all the data was in one block and it was all or
nothing;
> there was no ability to pick which data to return. But in your
case of
> wanting to get to random locations, it would be difficult to
arrange things
> with an SPI control byte and clock edges coming in at 1 Mb/s
rates. In my
> slave, I also could restrict the master on the clock rate used, and
went
> only up to 100 Kb/s or so.
>
> Lou
>
> _________________________________________________________________
> Visit MSN Holiday Challenge for your chance to win up to $50,000 in
Holiday
> cash from MSN today!
> http://www.msnholidaychallenge.com/index.aspx?
ocid=tagline&locale=en-us
>
general. But it may still be possible under special circumstances.
For example, if the master always read the bytes in a certain order,
the slave can anticipate what to send without waiting for the address
of the byte.
Another example is, if the master reads a block of bytes with some
kind of error checking. In this case, the slave could introduce
errors to force the master to re-read the block with the same
address. This would slow down the process, but acceptable for some
applications.
--- In m..., "Lou C" wrote:
>
> John,
>
> I agree with Kip when he says:
>
> >You may be better off having multiple 25LC320 and selecting the
one you
> >want externally.
>
> In that way, there would not be firmware delays to worry about as
you will
> have with any micro-controller. I would bet most SPI slaves are
NOT
> micro-controllers but rather just logic (maybe programmable) that
can
> operate at very high speed.
>
> I once used an MSP430F169 to implement an SPI slave device. To be
a good
> SPI slave without a lot of timing problems, you will have to use
some DMA
> device and keep the clock rates low. On the 'F169, I used Port 1
to receive
> the slave enable signal from the master as an interrupt. That
interrupt
> would set up the DMA system. Then I wrote code to have a double
buffer
> where one buffer could be updated while the other was available for
the
> master.
>
> In my application, all the data was in one block and it was all or
nothing;
> there was no ability to pick which data to return. But in your
case of
> wanting to get to random locations, it would be difficult to
arrange things
> with an SPI control byte and clock edges coming in at 1 Mb/s
rates. In my
> slave, I also could restrict the master on the clock rate used, and
went
> only up to 100 Kb/s or so.
>
> Lou
>
> _________________________________________________________________
> Visit MSN Holiday Challenge for your chance to win up to $50,000 in
Holiday
> cash from MSN today!
> http://www.msnholidaychallenge.com/index.aspx?
ocid=tagline&locale=en-us
>
Reply by ●December 20, 20062006-12-20
There is also the LPC2101 from NXP. 70MHz operation and under $2 for
quantities of 100 or more.
Regards
-Bill Knight
R O SoftWare
old_cow_yellow wrote:
> I agree. To respond to READ, you only have one half of a SCK to do
> it. If SCK = 1 MHz and your CPU's MCLK is only 16 MHz that is very
> tight. MSP430 CPU takes more than 4 MCLKs to read/write memory or I/O
> registers (and only 1 MCLK to operating on CPU registers).
>
> Freescale S08 and S12 chips are faster. I think the CPU clock can be
> as high as 40 MHz. Timing for READ could still be tight.
>
> --- In m..., Kipton Moravec wrote:
>> The problem I see is the turn around time. You get a 16 bit address
> and
>> have to immediately have the data in the next clock (<1
> microsecond). It
>> is too fast a turn around for an interrupt driven system.
>>
>> There is a chance you could do it running at 16 MHz, polling on the
>> receive, as soon as the data arrives pull it from memory and stick
> it in
>> the SPI output register. You have to be really careful on the
>> instructions you use and you can only use a couple of assembler
>> instructions to do it.
>>
>> You may be better off having multiple 25LC320 and selecting the one
> you
>> want externally.
>>
>> The chip is cheap. $0.53.
>> http://ww1.microchip.com/downloads/en/DeviceDoc/21227E.pdf
>>
>> Kip
>>
>> On Tue, 2006-12-19 at 20:06 +0000, John Speth wrote:
>>>> I do not quite understand your situation. Is this "legacy
> device"
>>> the
>>>> same thing as the "smart sensor host"? In what way can MSP430
>>>> chip "support"?
>>> The legacy device is a family of products (I'll call them hosts)
> that
>>> our sensors connect to. The host reads the sensor EEPROM using
> SPI.
>>> We're upgrading the sensor products and we can't upgrade the host
>>> firmware.
>>>
>>> My goal is to replace the sensor's 25LC320 SPI EEPROM with an
> MSP430
>>> or other micro. It must perform the same SPI interface functions
> the
>>> EEPROM performs up to the SPI clock rate of 1 MHz.
>>>
>>>> Also, how many times do you need to erase/write the calibration
>>>> constants in the lifetime of the device? Can you use the
> internal
>>>> Flash of MSP430 instead of an external EEPROM?
>>> It's write once, read many. The MSP430 has plenty of flash space
> to
>>> store my data (I can use unsed code flash for that). I'm looking
> for
>>> a one-chip solution.
>>>
>>> JJS
>>>
>>>> --- In m..., "John Speth" wrote:
>>>>> Hi Group-
>>>>>
>>>>> I'm hoping to tap into your various experiences regarding a
>>>> specific
>>>>> application I am being asked to consider:
>>>>>
>>>>> We would like to support a legacy device that in the past was
>>>> simply
>>>>> an EEPROM (25LC320 SPI compatible 4K bytes). It holds sensor
>>>>> calibration data. When a sensor is connected to the smart
> sensor
>>>>> host, the host reads the EEPROM data. Now we want to make the
>>>> sensor
>>>>> a little smarter. We want to be able to select cal data sets
>>>>> presented by the EEPROM depending on sensor characteristics
> that
>>>>> change dynamically. We need to support SPI clock rates up to
> 1
>>> MHz.
>>>>> I am looking into whether an MSP430 (or some other
>>> micrcontroller)
>>>>> can emulate the 25LC320 EEPROM SPI interface reliably. Has
>>> anyone
>>>>> ever tried this?
>>>>>
>>>>> From my investigation I see one problem that is related to
> the
>>> read
>>>>> byte cycle - To read a byte, the SPI master sends a READ
> opcode
>>>> byte,
>>>>> followed by 16 bits of address, followed by 8 clocks that
> will
>>>> clock
>>>>> in data to the master on MISO. I can't envision that the
> MSP430
>>>> can
>>>>> resolve the opcode and address fast enough so that the data
> is
>>>> ready
>>>>> in the MSP430 transmit buffer by the time the first clock of
> the
>>>> last
>>>>> 8 clocks for read byte data is received.
>>>>>
>>>>> A huge constraint on the system is that I can't control the
> rate
>>> of
>>>>> clocks from the SPI master (but will not exceed 1 MHz). The
>>> MSP430
>>>>> needs to be ready with data on demand. If the MSP430 isn't
>>>> suitable
>>>>> for the task, can anyone suggest a mictrocontroller that is?
>>>>>
>>>>> Thanks for your expert opinions, John.
>>>>>
>> --
>> Kipton Moravec
quantities of 100 or more.
Regards
-Bill Knight
R O SoftWare
old_cow_yellow wrote:
> I agree. To respond to READ, you only have one half of a SCK to do
> it. If SCK = 1 MHz and your CPU's MCLK is only 16 MHz that is very
> tight. MSP430 CPU takes more than 4 MCLKs to read/write memory or I/O
> registers (and only 1 MCLK to operating on CPU registers).
>
> Freescale S08 and S12 chips are faster. I think the CPU clock can be
> as high as 40 MHz. Timing for READ could still be tight.
>
> --- In m..., Kipton Moravec wrote:
>> The problem I see is the turn around time. You get a 16 bit address
> and
>> have to immediately have the data in the next clock (<1
> microsecond). It
>> is too fast a turn around for an interrupt driven system.
>>
>> There is a chance you could do it running at 16 MHz, polling on the
>> receive, as soon as the data arrives pull it from memory and stick
> it in
>> the SPI output register. You have to be really careful on the
>> instructions you use and you can only use a couple of assembler
>> instructions to do it.
>>
>> You may be better off having multiple 25LC320 and selecting the one
> you
>> want externally.
>>
>> The chip is cheap. $0.53.
>> http://ww1.microchip.com/downloads/en/DeviceDoc/21227E.pdf
>>
>> Kip
>>
>> On Tue, 2006-12-19 at 20:06 +0000, John Speth wrote:
>>>> I do not quite understand your situation. Is this "legacy
> device"
>>> the
>>>> same thing as the "smart sensor host"? In what way can MSP430
>>>> chip "support"?
>>> The legacy device is a family of products (I'll call them hosts)
> that
>>> our sensors connect to. The host reads the sensor EEPROM using
> SPI.
>>> We're upgrading the sensor products and we can't upgrade the host
>>> firmware.
>>>
>>> My goal is to replace the sensor's 25LC320 SPI EEPROM with an
> MSP430
>>> or other micro. It must perform the same SPI interface functions
> the
>>> EEPROM performs up to the SPI clock rate of 1 MHz.
>>>
>>>> Also, how many times do you need to erase/write the calibration
>>>> constants in the lifetime of the device? Can you use the
> internal
>>>> Flash of MSP430 instead of an external EEPROM?
>>> It's write once, read many. The MSP430 has plenty of flash space
> to
>>> store my data (I can use unsed code flash for that). I'm looking
> for
>>> a one-chip solution.
>>>
>>> JJS
>>>
>>>> --- In m..., "John Speth" wrote:
>>>>> Hi Group-
>>>>>
>>>>> I'm hoping to tap into your various experiences regarding a
>>>> specific
>>>>> application I am being asked to consider:
>>>>>
>>>>> We would like to support a legacy device that in the past was
>>>> simply
>>>>> an EEPROM (25LC320 SPI compatible 4K bytes). It holds sensor
>>>>> calibration data. When a sensor is connected to the smart
> sensor
>>>>> host, the host reads the EEPROM data. Now we want to make the
>>>> sensor
>>>>> a little smarter. We want to be able to select cal data sets
>>>>> presented by the EEPROM depending on sensor characteristics
> that
>>>>> change dynamically. We need to support SPI clock rates up to
> 1
>>> MHz.
>>>>> I am looking into whether an MSP430 (or some other
>>> micrcontroller)
>>>>> can emulate the 25LC320 EEPROM SPI interface reliably. Has
>>> anyone
>>>>> ever tried this?
>>>>>
>>>>> From my investigation I see one problem that is related to
> the
>>> read
>>>>> byte cycle - To read a byte, the SPI master sends a READ
> opcode
>>>> byte,
>>>>> followed by 16 bits of address, followed by 8 clocks that
> will
>>>> clock
>>>>> in data to the master on MISO. I can't envision that the
> MSP430
>>>> can
>>>>> resolve the opcode and address fast enough so that the data
> is
>>>> ready
>>>>> in the MSP430 transmit buffer by the time the first clock of
> the
>>>> last
>>>>> 8 clocks for read byte data is received.
>>>>>
>>>>> A huge constraint on the system is that I can't control the
> rate
>>> of
>>>>> clocks from the SPI master (but will not exceed 1 MHz). The
>>> MSP430
>>>>> needs to be ready with data on demand. If the MSP430 isn't
>>>> suitable
>>>>> for the task, can anyone suggest a mictrocontroller that is?
>>>>>
>>>>> Thanks for your expert opinions, John.
>>>>>
>> --
>> Kipton Moravec
Reply by ●December 20, 20062006-12-20
tHERE ARE WAYS AROUND HAVING TO READ OR TEST PINS DIRECTLY, on what appears to
be a simple design, by this I mean in terms of function, not implementation on
an MSP430. My reckoning suggests 1 port for the SPi clk and slave In signals and
the other port for I/O functions and the SLAVE OUT signal. By arranging for the
clk signal (I'm assuming active high here) to be on P2.2 and the MOSI
signal to be on P2.1, AND FOR the rest of P2 to be unused, pulled low, you could
use a cheat like:_
READx:
ADD &P2IN,PC ; 3 CLKS ACCORDING TO CHAPTER 5 CLRS CARRY
JMP READx ;NO CLK HIGH SO STALL
JMP READx ;NO CLK HIGH, IGNORE MISO
JMP BITIS0 ;CLK IS HIGH Mosi IS LOW
SETC ;CLK AND Mosi ARE HIGH
BITIS0:
RLC R4 ;ROTATE ADDRESS INTO RESERVED REG
WAITx:
ADD &P2IN,PC ;CAN'T ADVANCE UNTIL CLOCK RETURNS TO LOW
JMP READy ;CLK LOW ADVANCE TO NEXT BIT
JMP READy
JMP WAITx ;STALL UNTIL CLOCK GOES LOW
JMP WAITx
READy:
This is faster than the ISR latency, and faster to handle I/O. I don't intend it as a solution, since there would be an issue in data output, but it indicates how a different approach may be used. In the example above the code would be inlined for each of the 16 address bits, ie no loops. The read section takes 5 clocks in the case of no input clock or a low data bit, and 4 in the case of a high data bit. The exit section takes 5 clocks regardless. After the 16th bit you could use MOV 0(R4),&P1OUT, where SLAVE OUT is on P1.0, and ONLY p1.0 is enabled as an output at this time. in which case the data input code becomes a matter of shifting the data byte through the P1OUT register, this would make the data input code require 9 or 10 data clocks per bit, with JUST 6 clocks spare to move the data byte from memory to the P1OUT register after the address has been read, and the output code to require a total of 11 clock cycles per bit. On /CS going low the micro would set P1DIR to 0x01, and disable INTS, and reset it to normal operation on /CS going high.
Thus it is just about possible to implement the required emulator on an MSP430, providing the addresses are linear, and mapped to MSP430 address space, without overclocking, and assuming certain characteristics of the Master SPI unit, but I'd rather wait for the 25MHz or faster parts to come along.
Cheers
Al
John,
I agree with Kip when he says:
>>You may be better off having multiple 25LC320 and selecting the one you
>>want externally.
In that way, there would not be firmware delays to worry about as you will
have with any micro-controller. I would bet most SPI slaves are NOT
micro-controllers but rather just logic (maybe programmable) that can
operate at very high speed.
I once used an MSP430F169 to implement an SPI slave device. To be a good
SPI slave without a lot of timing problems, you will have to use some DMA
device and keep the clock rates low. On the 'F169, I used Port 1 to receive
the slave enable signal from the master as an interrupt. That interrupt
would set up the DMA system. Then I wrote code to have a double buffer
where one buffer could be updated while the other was available for the
master.
In my application, all the data was in one block and it was all or nothing;
there was no ability to pick which data to return. But in your case of
wanting to get to random locations, it would be difficult to arrange things
with an SPI control byte and clock edges coming in at 1 Mb/s rates. In my
slave, I also could restrict the master on the clock rate used, and went
only up to 100 Kb/s or so.
Lou
_
READx:
ADD &P2IN,PC ; 3 CLKS ACCORDING TO CHAPTER 5 CLRS CARRY
JMP READx ;NO CLK HIGH SO STALL
JMP READx ;NO CLK HIGH, IGNORE MISO
JMP BITIS0 ;CLK IS HIGH Mosi IS LOW
SETC ;CLK AND Mosi ARE HIGH
BITIS0:
RLC R4 ;ROTATE ADDRESS INTO RESERVED REG
WAITx:
ADD &P2IN,PC ;CAN'T ADVANCE UNTIL CLOCK RETURNS TO LOW
JMP READy ;CLK LOW ADVANCE TO NEXT BIT
JMP READy
JMP WAITx ;STALL UNTIL CLOCK GOES LOW
JMP WAITx
READy:
This is faster than the ISR latency, and faster to handle I/O. I don't intend it as a solution, since there would be an issue in data output, but it indicates how a different approach may be used. In the example above the code would be inlined for each of the 16 address bits, ie no loops. The read section takes 5 clocks in the case of no input clock or a low data bit, and 4 in the case of a high data bit. The exit section takes 5 clocks regardless. After the 16th bit you could use MOV 0(R4),&P1OUT, where SLAVE OUT is on P1.0, and ONLY p1.0 is enabled as an output at this time. in which case the data input code becomes a matter of shifting the data byte through the P1OUT register, this would make the data input code require 9 or 10 data clocks per bit, with JUST 6 clocks spare to move the data byte from memory to the P1OUT register after the address has been read, and the output code to require a total of 11 clock cycles per bit. On /CS going low the micro would set P1DIR to 0x01, and disable INTS, and reset it to normal operation on /CS going high.
Thus it is just about possible to implement the required emulator on an MSP430, providing the addresses are linear, and mapped to MSP430 address space, without overclocking, and assuming certain characteristics of the Master SPI unit, but I'd rather wait for the 25MHz or faster parts to come along.
Cheers
Al
John,
I agree with Kip when he says:
>>You may be better off having multiple 25LC320 and selecting the one you
>>want externally.
In that way, there would not be firmware delays to worry about as you will
have with any micro-controller. I would bet most SPI slaves are NOT
micro-controllers but rather just logic (maybe programmable) that can
operate at very high speed.
I once used an MSP430F169 to implement an SPI slave device. To be a good
SPI slave without a lot of timing problems, you will have to use some DMA
device and keep the clock rates low. On the 'F169, I used Port 1 to receive
the slave enable signal from the master as an interrupt. That interrupt
would set up the DMA system. Then I wrote code to have a double buffer
where one buffer could be updated while the other was available for the
master.
In my application, all the data was in one block and it was all or nothing;
there was no ability to pick which data to return. But in your case of
wanting to get to random locations, it would be difficult to arrange things
with an SPI control byte and clock edges coming in at 1 Mb/s rates. In my
slave, I also could restrict the master on the clock rate used, and went
only up to 100 Kb/s or so.
Lou
_
Reply by ●December 20, 20062006-12-20
On 2006-12-20, Lou C wrote:
> I agree with Kip when he says:
>
>>You may be better off having multiple 25LC320 and selecting the
>>one you want externally.
What you really want is dual-ported SPI RAM. Sort of.
Not that I'm aware of such a thing existing off-the-shelf, but
you might be able to gen one up with a programmable logic
device.
--
Grant Edwards grante Yow! On the road, ZIPPY
at is a pinhead without a
visi.com purpose, but never without
a POINT.
> I agree with Kip when he says:
>
>>You may be better off having multiple 25LC320 and selecting the
>>one you want externally.
What you really want is dual-ported SPI RAM. Sort of.
Not that I'm aware of such a thing existing off-the-shelf, but
you might be able to gen one up with a programmable logic
device.
--
Grant Edwards grante Yow! On the road, ZIPPY
at is a pinhead without a
visi.com purpose, but never without
a POINT.
Reply by ●December 20, 20062006-12-20
On 2006-12-20, Grant Edwards wrote:
> On 2006-12-20, Lou C wrote:
>
>> I agree with Kip when he says:
>>
>>>You may be better off having multiple 25LC320 and selecting the
>>>one you want externally.
>
> What you really want is dual-ported SPI RAM. Sort of.
>
> Not that I'm aware of such a thing existing off-the-shelf, but
> you might be able to gen one up with a programmable logic
> device.
I did notice a dual-ported I2C EEPROM at Catalyst
Semiconductor's web site. They didn't appear to have an SPI
version available.
I doubt an off-the-shelf part would work anyway since you
probably need to do some sort of page-flipping to make sure the
other SPI master would always see a consistent set of data.
Even that probably won't work if the other master uses SPI
transactions to read the data.
--
Grant Edwards grante Yow! Here I am in 53
at B.C. and all I want is a
visi.com dill pickle!!
> On 2006-12-20, Lou C wrote:
>
>> I agree with Kip when he says:
>>
>>>You may be better off having multiple 25LC320 and selecting the
>>>one you want externally.
>
> What you really want is dual-ported SPI RAM. Sort of.
>
> Not that I'm aware of such a thing existing off-the-shelf, but
> you might be able to gen one up with a programmable logic
> device.
I did notice a dual-ported I2C EEPROM at Catalyst
Semiconductor's web site. They didn't appear to have an SPI
version available.
I doubt an off-the-shelf part would work anyway since you
probably need to do some sort of page-flipping to make sure the
other SPI master would always see a consistent set of data.
Even that probably won't work if the other master uses SPI
transactions to read the data.
--
Grant Edwards grante Yow! Here I am in 53
at B.C. and all I want is a
visi.com dill pickle!!
