I am unable to see any output from MCLK (pin 48 on an Msp- fet430p140). I tried to set P5 to be an output ... P5 = 0x0F, but still see no MCLK. Any ideas?
MCLK output
Started by ●June 28, 2002
Reply by ●June 28, 20022002-06-28
--- In msp430@y..., "cteise" <clyde.eisenbeis@e...> wrote:
> I am unable to see any output from MCLK (pin 48 on
an Msp-
> fet430p140). I tried to set P5 to be an output ... P5 = 0x0F, but
> still see no MCLK. Any ideas?
You must also set same bit in the P5SEL register to change the output
of the pin from a standard I/O to its "alternate function", i.e.
output of the MCLK.
Chris
Reply by ●July 1, 20022002-07-01
Thanks Chris. Made the change ... still no MCLK. I'm
quite confident the code is downloading and running properly ... I modified the
blinking LED sample code (fet140_1.c) ... the LED blinks, but still no
MCLK.
-----Original Message-------- In msp430@y..., "cteise" <clyde.eisenbeis@e...> wrote:
From: dellaenterprises [mailto:dellaenterprises@prodigy.net]
Sent: Friday, June 28, 2002 5:47 PM
To: msp430@yahoogroups.com
Subject: [msp430] Re: MCLK output
> I am unable to see any output from MCLK (pin 48 on an Msp-
> fet430p140). I tried to set P5 to be an output ... P5 = 0x0F, but
> still see no MCLK. Any ideas?
You must also set same bit in the P5SEL register to change the output
of the pin from a standard I/O to its "alternate function", i.e.
output of the MCLK.
Chris
">Yahoo! Terms of Service.
Reply by ●July 1, 20022002-07-01
Clyde,
An example
is at TI's web site http://www.ti.com/sc/msp430
>>> Code Examples
MSP-FET430P140 Assembler Examples slac014x.zip
(38k)
- fet140_clks.s43 - BasicClock Output buffered SMCLK, ACLK and MCLK
Regards
Peter
-----Original
Message-----
From: Eisenbeis, Clyde [FRCO/MTN] [mailto:clyde.eisenbeis@emersonprocess.com]
Sent: Monday, 01 July, 2002 15:43
To: 'msp430@yahoogroups.com'
Subject: RE: [msp430] Re: MCLK output
From: Eisenbeis, Clyde [FRCO/MTN] [mailto:clyde.eisenbeis@emersonprocess.com]
Sent: Monday, 01 July, 2002 15:43
To: 'msp430@yahoogroups.com'
Subject: RE: [msp430] Re: MCLK output
Thanks Chris. Made the change ... still no MCLK. I'm
quite confident the code is downloading and running properly ... I modified the
blinking LED sample code (fet140_1.c) ... the LED blinks, but still no
MCLK.
-----Original Message-------- In msp430@y..., "cteise" <clyde.eisenbeis@e...> wrote:
From: dellaenterprises [mailto:dellaenterprises@prodigy.net]
Sent: Friday, June 28, 2002 5:47 PM
To: msp430@yahoogroups.com
Subject: [msp430] Re: MCLK output
> I am unable to see any output from MCLK (pin 48 on an Msp-
> fet430p140). I tried to set P5 to be an output ... P5 = 0x0F, but
> still see no MCLK. Any ideas?
You must also set same bit in the P5SEL register to change the output
of the pin from a standard I/O to its "alternate function", i.e.
output of the MCLK.
Chris
">Yahoo! Terms of Service.
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Reply by ●July 1, 20022002-07-01
Thanks Peter ... I have it straight now.
In the docs, my sense is that slow freq crystals should use Xin and
high freq crystals should use Xt2in. Yet the fet140_clks.s43 uses a high
freq crystal on Xin. Is there any advantage of using Xin over Xt2in
(assuming I don't need an ACLK)?
I stuck a 1Mhz crystal across Xt2in with a couple of 68pf caps (did not
have any 64pf caps). The crystal appears to be oscillating ok, but I
can't get anything out of MCLK except for the DCO. The instructions I
am using to switch MCLK to Xt2clk are:
BCSCTL1 &= ~XT2OFF;
BCSCTL2 |= SELM_2;
BCSCTL2 |= SELM_2;
Any suggestions?
Clyde
-----Original Message-----
From: Forstner, Peter [mailto:msp430@onlinehome.de]
Sent: Monday, July 01, 2002 9:31 AM
To: 'msp430@yahoogroups.com'
Subject: RE: [msp430] Re: MCLK outputClyde,An example is at TI's web site http://www.ti.com/sc/msp430 >>> Code ExamplesMSP-FET430P140 Assembler Examples slac014x.zip (38k)
- fet140_clks.s43 - BasicClock Output buffered SMCLK, ACLK and MCLK
RegardsPeter-----Original Message-----
From: Eisenbeis, Clyde [FRCO/MTN] [mailto:clyde.eisenbeis@emersonprocess.com]
Sent: Monday, 01 July, 2002 15:43
To: 'msp430@yahoogroups.com'
Subject: RE: [msp430] Re: MCLK outputThanks Chris. Made the change ... still no MCLK. I'm quite confident the code is downloading and running properly ... I modified the blinking LED sample code (fet140_1.c) ... the LED blinks, but still no MCLK.-----Original Message-------- In msp430@y..., "cteise" <clyde.eisenbeis@e...> wrote:
From: dellaenterprises [mailto:dellaenterprises@prodigy.net]
Sent: Friday, June 28, 2002 5:47 PM
To: msp430@yahoogroups.com
Subject: [msp430] Re: MCLK output
> I am unable to see any output from MCLK (pin 48 on an Msp-
> fet430p140). I tried to set P5 to be an output ... P5 = 0x0F, but
> still see no MCLK. Any ideas?
You must also set same bit in the P5SEL register to change the output
of the pin from a standard I/O to its "alternate function", i.e.
output of the MCLK.
Chris
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Reply by ●July 1, 20022002-07-01
Hi Clyde,
A few pointers :
1. When you use a "high frequency" crystal on LFXTAL1
(XT1) you have to set the XTS bit in BCSCTL1.
2. You have to account for the oscillator fault
circuitry.
If the clock fails, the CPU would
enter an irrecoverable state. Conversely, on startup the MSP430 defaults to the
DCO.
3. If you switch to XT2 for MCLK, the OFIFG flag is
still set (after power up the crystal oscillators aren't running yet, the
DCO
is however) - So the CPU
will straight away switch back to DCO as its MCLK, because it thimks
there's still an OSC fault
You first need to clear OFIFG before
switching clock.
The best sequence to switch from DCO to
XT2 for MCLK is :
/* either wait enough time for XT2 ( + opt XT1) to settle
*/
// wait XXX mS clocked with the DCO ...........
OR
do (IFG1 &=~OFIFG)
while (IFG1&OFIFG); /* wait till
oscillator(s) have stabilised......
AND/OR NOW
IFG1&=~OFIFG;
/* case just used delay, clear the oscillator fault flag
*/
BCSCTL1 &=
~XT2OFF; /* now swicth your clock from DCO
-> XT2 */
BCSCTL2 |= SELM_2;
BCSCTL2 |= SELM_2;
That'll work 100% for
you.
PS :
OFIFG flag clearing means
that the XT2 has been running for (I think) 100 consecutive cycles without
fault.
It does not mean its
frequency is accurate. (as a rule of fist, it takes Q cycles to
stabilise)
As a rough guide, depending
on crystal ESR (low profile HC49 has higher ESR) it takes ~ 5-6 mS to
stabilise
an 6 MHz crystal on
XT2.
It also depends on the
phase shift network (loading caps) and the loading capacitance of your
crystal.
I wouldn't worry too
much about the 64 vs. 68 pF caps, you crystal probably has different
characteristics anyway.
Kris
----- Original Message -----From: Eisenbeis, Clyde [FRCO/MTN]To: 'msp430@yahoogroups.com'Sent: Tuesday, July 02, 2002 7:41 AMSubject: RE: [msp430] Re: MCLK outputThanks Peter ... I have it straight now.In the docs, my sense is that slow freq crystals should use Xin and high freq crystals should use Xt2in. Yet the fet140_clks.s43 uses a high freq crystal on Xin. Is there any advantage of using Xin over Xt2in (assuming I don't need an ACLK)?I stuck a 1Mhz crystal across Xt2in with a couple of 68pf caps (did not have any 64pf caps). The crystal appears to be oscillating ok, but I can't get anything out of MCLK except for the DCO. The instructions I am using to switch MCLK to Xt2clk are:BCSCTL1 &= ~XT2OFF;
BCSCTL2 |= SELM_2;Any suggestions?Clyde-----Original Message-----
From: Forstner, Peter [mailto:msp430@onlinehome.de]
Sent: Monday, July 01, 2002 9:31 AM
To: 'msp430@yahoogroups.com'
Subject: RE: [msp430] Re: MCLK outputClyde,An example is at TI's web site http://www.ti.com/sc/msp430 >>> Code ExamplesMSP-FET430P140 Assembler Examples slac014x.zip (38k)
- fet140_clks.s43 - BasicClock Output buffered SMCLK, ACLK and MCLK
RegardsPeter-----Original Message-----
From: Eisenbeis, Clyde [FRCO/MTN] [mailto:clyde.eisenbeis@emersonprocess.com]
Sent: Monday, 01 July, 2002 15:43
To: 'msp430@yahoogroups.com'
Subject: RE: [msp430] Re: MCLK outputThanks Chris. Made the change ... still no MCLK. I'm quite confident the code is downloading and running properly ... I modified the blinking LED sample code (fet140_1.c) ... the LED blinks, but still no MCLK.-----Original Message-------- In msp430@y..., "cteise" <clyde.eisenbeis@e...> wrote:
From: dellaenterprises [mailto:dellaenterprises@prodigy.net]
Sent: Friday, June 28, 2002 5:47 PM
To: msp430@yahoogroups.com
Subject: [msp430] Re: MCLK output
> I am unable to see any output from MCLK (pin 48 on an Msp-
> fet430p140). I tried to set P5 to be an output ... P5 = 0x0F, but
> still see no MCLK. Any ideas?
You must also set same bit in the P5SEL register to change the output
of the pin from a standard I/O to its "alternate function", i.e.
output of the MCLK.
Chris
">Yahoo! Terms of Service.
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">Yahoo! Terms of Service.
Reply by ●July 2, 20022002-07-02
I agree with "Kris De Vos" in that you aren't actually switching MCLK to XT2 because of the Oscillator Fault. There are TI examples on using XT2 (and therefore switching XT2 to MCLK) ... find them and you'll be learning. Kris handed you nearly plug-and-play code, patch that together with the Module Guide and some examples ... then re- post your "victory".
Reply by ●July 2, 20022002-07-02
I in turn agree with CP8071 !
It's a tough one..
On one hand people should learn these things for themselves.
(SLAU049 User's guide ...... 7.4.4 --- Selecting a crystal clock for
MCLK)
On the other hand, why have them spending (wasting) hours of sniffing thru
manuals
over things we've already done ?
This way they actually get to concentrate on their "app", and TI gets
more
design wins, and that's partially what I'm here for too.
(Although TI doesn't pay me for that !!!!!!!!)
I like helping people though, and there's still a loooot of "secrets"
to discover or work through
with F13X/F14X, if people want help there, well they'll be paying me
for it !!!!!!!!!
My main revenue is RF though, so it's not "stealing my crust"
:-)
Wait till you really squeeze the "max" out of a F149 with all resources
used, you're in for a good one
(I have) .........
Kris
----- Original Message -----From: CP8071To: msp430@yahoogroups.comSent: Tuesday, July 02, 2002 1:27 PMSubject: [msp430] Re: MCLK output
I agree with "Kris De Vos" in that you aren't actually switching MCLK
to XT2 because of the Oscillator Fault. There are TI examples on
using XT2 (and therefore switching XT2 to MCLK) ... find them and
you'll be learning. Kris handed you nearly plug-and-play code, patch
that together with the Module Guide and some examples ... then re-
post your "victory".
">Yahoo! Terms of Service.
Reply by ●July 3, 20022002-07-03
Hi,
An example that helped me a lot was the easyweb app. Which is downloadable. In that app note it states very clear how to use the xt2 and that in conjunction with the manual cleared that part for me. Here's an example on using the xt2 for mclk.
Success
Martijn
// enables the 8MHz crystal on XT2 and use
// it as MCLK
void InitOsc(void)
{
unsigned int i;
WDTCTL = WDTPW + WDTHOLD; // Stop WDT
BCSCTL1 &= ~XT2OFF; // XT2on
do
{
IFG1 &~OFIFG; // Clear OSCFault flag
for (i = 0xFF; i > 0; i--); // Time for flag to set
}
while ((IFG1 & OFIFG) != 0); // OSCFault flag still set?
BCSCTL1 |= DIVA0; // ACLK = XT2 / 2 = 4MHz
BCSCTL1 &= ~DIVA1;
BCSCTL2 |= SELM1+SELS; // MCLK XT2 = 8MHz
// SMCLK = XT2/8 = 1MHz
IE1 &= ~WDTIE; // disable WDT int.
IFG1 &= ~WDTIFG; // clear WDT int. flag
WDTCTL = WDT_MDLY_0_5 ; // 0.5ms
// WDT-interval times [1ms] coded with Bits 0-2
// WDT is clocked by fMCLK (assumed 1MHz)
while (!(IFG1 & WDTIFG)); // count 1024 pulses from XT1 (until XT1's
// amplitude is OK)
IFG1 &= ~OFIFG; // clear osc. fault int. flag
}
met vriendelijke groet,
Abiom-MBT b.v.
Martijn Broens
Kerkenbos 10-93
NL-6546 BB Nijmegen
Tel: +31 24 373 4422
Fax: +31 24 378 4888
mailto:martijn@abiom.nl
-----Oorspronkelijk
bericht-----
Van: Kris De Vos
[mailto:microbit@cyberspace.net.au]
Verzonden: dinsdag 2 juli 2002
5:45
Aan: msp430@yahoogroups.com
Onderwerp: Re: [msp430] Re: MCLK
output
I in turn agree with CP8071 !
It's a tough one..
On one hand people should learn these things for themselves.
(SLAU049 User's guide ...... 7.4.4 --- Selecting a crystal clock for MCLK)
On the other hand, why have them spending (wasting) hours of sniffing thru manuals
over things we've already done ?
This way they actually get to concentrate on their "app", and TI gets more
design wins, and that's partially what I'm here for too.
(Although TI doesn't pay me for that !!!!!!!!)
I like helping people though, and there's still a loooot of "secrets" to discover or work through
with F13X/F14X, if people want help there, well they'll be paying me for it !!!!!!!!!
My main revenue is RF though, so it's not "stealing my crust" :-)
Wait till you really squeeze the "max" out of a F149 with all resources used, you're in for a good one
(I have) .........
Kris
----- Original Message -----
From: CP8071
To: msp430@yahoogroups.com
Sent: Tuesday, July 02, 2002 1:27 PM
Subject: [msp430] Re: MCLK output
I agree with "Kris De Vos" in that you aren't actually switching MCLK
to XT2 because of the Oscillator Fault. There are TI examples on
using XT2 (and therefore switching XT2 to MCLK) ... find them and
you'll be learning. Kris handed you nearly plug-and-play code, patch
that together with the Module Guide and some examples ... then re-
post your "victory".
To unsubscribe from the msp430 group, send an email to:
msp430-unsubscribe@egroups.com
">Yahoo! Terms of Service.
To
unsubscribe from the msp430 group, send an email to:
msp430-unsubscribe@egroups.com
">Yahoo!
Terms of Service.
Reply by ●July 3, 20022002-07-03
Hi Kris,
Thanks for the clear, concise description.
If ACLK is not needed, is there any advantage /
disadvantage with using Xin instead of Xt2in for a high freq
clock?
For my future reference, and perhaps for others, I
would like to create descriptions / snippets of sample code for each of the
crystal combinations. Please make additions / corrections to the
following.
----
Crystal freq ranges:
low
freq crystal: 32.768 Khz ... min / max ???
high
freq crystal: 1 Mhz - 8 Mhz
Setup:
WDTCTL = WDTPW + WDTHOLD; // Stop
watchdog timer
//Next two instructions give ability to watch the clocks on a scope
P5DIR = 0xFF; //Set P5 to output direction
P5SEL = 0xFF; //Set P5 to output MCLK, ACLK, etc.
//Next two instructions give ability to watch the clocks on a scope
P5DIR = 0xFF; //Set P5 to output direction
P5SEL = 0xFF; //Set P5 to output MCLK, ACLK, etc.
Case
1: No crystals ... use DCO
Advantage:
no external parts
Disadvantage: freq may not be stable
Default
condition after power up ... around 750 Khz
Case
2: One low freq crystal on Xin
Advantage:
lowest power consumption
Disadvantage:
???
do
(IFG1 &= ~OFIFG)
while (IFG1 & OFIFG); //Wait until oscillator has stabilized
IFG1 &= ~OFIFG; //Clear the oscillator fault flag
BCSCTL1 &= ~XTS; //Set Xin to low freq
BCSCTL2 |= SELM_3; //Set MCLK to use Xin
while (IFG1 & OFIFG); //Wait until oscillator has stabilized
IFG1 &= ~OFIFG; //Clear the oscillator fault flag
BCSCTL1 &= ~XTS; //Set Xin to low freq
BCSCTL2 |= SELM_3; //Set MCLK to use Xin
Case
3: One high freq crystal on Xin
Advantage:
???
Disadvantage:
???
do
(IFG1 &= ~OFIFG)
while (IFG1 & OFIFG); //Wait until oscillator has stabilized
IFG1 &= ~OFIFG; //Clear the oscillator fault flag
BCSCTL1 |= XTS; //Set Xin to high freq
BCSCTL2 |= SELM_3; //Set MCLK to use Xin
while (IFG1 & OFIFG); //Wait until oscillator has stabilized
IFG1 &= ~OFIFG; //Clear the oscillator fault flag
BCSCTL1 |= XTS; //Set Xin to high freq
BCSCTL2 |= SELM_3; //Set MCLK to use Xin
Case 4: One high freq crystal on
Xt2in
Advantage: ???
Disadvantage: No Aux
Clock
do
(IFG1 &= ~OFIFG)
while (IFG1 & OFIFG); //Wait until oscillator has stabilized
IFG1 &= ~OFIFG; //Clear the oscillator fault flag
BCSCTL1 &= ~XT2OFF; //Set Xt2in on
BCSCTL2 |= SELM_2; //Set MCLK to use Xt2in
while (IFG1 & OFIFG); //Wait until oscillator has stabilized
IFG1 &= ~OFIFG; //Clear the oscillator fault flag
BCSCTL1 &= ~XT2OFF; //Set Xt2in on
BCSCTL2 |= SELM_2; //Set MCLK to use Xt2in
Case 5: One low freq crystal on Xin and one
high freq crystal on Xt2in
Advantage:
???
Disadvantage:
???
do
(IFG1 &= ~OFIFG)
while (IFG1 & OFIFG); //Wait until oscillator has stabilized
IFG1 &= ~OFIFG; //Clear the oscillator fault flag
BCSCTL1 &= ~XTS; //Set Xin to low freq
BCSCTL1 &= ~XT2OFF; //Set Xt2in on
BCSCTL2 |= SELM_3; //Set MCLK to use Xin
while (IFG1 & OFIFG); //Wait until oscillator has stabilized
IFG1 &= ~OFIFG; //Clear the oscillator fault flag
BCSCTL1 &= ~XTS; //Set Xin to low freq
BCSCTL1 &= ~XT2OFF; //Set Xt2in on
BCSCTL2 |= SELM_3; //Set MCLK to use Xin
...
BCSCTL2 |= SELM_2; //Set MCLK to use Xt2in
...
BCSCTL2 |= SELM_3; //Set MCLK to use Xin
----
-----Original Message-----
From: Kris De Vos [mailto:microbit@cyberspace.net.au]
Sent: Monday, July 01, 2002 8:41 PM
To: msp430@yahoogroups.com
Subject: Re: [msp430] Re: MCLK outputHi Clyde,A few pointers :1. When you use a "high frequency" crystal on LFXTAL1 (XT1) you have to set the XTS bit in BCSCTL1.2. You have to account for the oscillator fault circuitry.If the clock fails, the CPU would enter an irrecoverable state. Conversely, on startup the MSP430 defaults to the DCO.3. If you switch to XT2 for MCLK, the OFIFG flag is still set (after power up the crystal oscillators aren't running yet, the DCOis however) - So the CPU will straight away switch back to DCO as its MCLK, because it thimks there's still an OSC faultYou first need to clear OFIFG before switching clock.The best sequence to switch from DCO to XT2 for MCLK is :/* either wait enough time for XT2 ( + opt XT1) to settle */// wait XXX mS clocked with the DCO ...........ORdo (IFG1 &=~OFIFG)while (IFG1&OFIFG); /* wait till oscillator(s) have stabilised......AND/OR NOWIFG1&=~OFIFG; /* case just used delay, clear the oscillator fault flag */BCSCTL1 &= ~XT2OFF; /* now swicth your clock from DCO -> XT2 */
BCSCTL2 |= SELM_2;That'll work 100% for you.PS :OFIFG flag clearing means that the XT2 has been running for (I think) 100 consecutive cycles without fault.It does not mean its frequency is accurate. (as a rule of fist, it takes Q cycles to stabilise)As a rough guide, depending on crystal ESR (low profile HC49 has higher ESR) it takes ~ 5-6 mS to stabilisean 6 MHz crystal on XT2.It also depends on the phase shift network (loading caps) and the loading capacitance of your crystal.I wouldn't worry too much about the 64 vs. 68 pF caps, you crystal probably has different characteristics anyway.Kris----- Original Message -----From: Eisenbeis, Clyde [FRCO/MTN]To: 'msp430@yahoogroups.com'Sent: Tuesday, July 02, 2002 7:41 AMSubject: RE: [msp430] Re: MCLK outputThanks Peter ... I have it straight now.In the docs, my sense is that slow freq crystals should use Xin and high freq crystals should use Xt2in. Yet the fet140_clks.s43 uses a high freq crystal on Xin. Is there any advantage of using Xin over Xt2in (assuming I don't need an ACLK)?I stuck a 1Mhz crystal across Xt2in with a couple of 68pf caps (did not have any 64pf caps). The crystal appears to be oscillating ok, but I can't get anything out of MCLK except for the DCO. The instructions I am using to switch MCLK to Xt2clk are:BCSCTL1 &= ~XT2OFF;
BCSCTL2 |= SELM_2;Any suggestions?Clyde-----Original Message-----
From: Forstner, Peter [mailto:msp430@onlinehome.de]
Sent: Monday, July 01, 2002 9:31 AM
To: 'msp430@yahoogroups.com'
Subject: RE: [msp430] Re: MCLK outputClyde,An example is at TI's web site http://www.ti.com/sc/msp430 >>> Code ExamplesMSP-FET430P140 Assembler Examples slac014x.zip (38k)
- fet140_clks.s43 - BasicClock Output buffered SMCLK, ACLK and MCLK
RegardsPeter-----Original Message-----
From: Eisenbeis, Clyde [FRCO/MTN] [mailto:clyde.eisenbeis@emersonprocess.com]
Sent: Monday, 01 July, 2002 15:43
To: 'msp430@yahoogroups.com'
Subject: RE: [msp430] Re: MCLK outputThanks Chris. Made the change ... still no MCLK. I'm quite confident the code is downloading and running properly ... I modified the blinking LED sample code (fet140_1.c) ... the LED blinks, but still no MCLK.-----Original Message-------- In msp430@y..., "cteise" <clyde.eisenbeis@e...> wrote:
From: dellaenterprises [mailto:dellaenterprises@prodigy.net]
Sent: Friday, June 28, 2002 5:47 PM
To: msp430@yahoogroups.com
Subject: [msp430] Re: MCLK output
> I am unable to see any output from MCLK (pin 48 on an Msp-
> fet430p140). I tried to set P5 to be an output ... P5 = 0x0F, but
> still see no MCLK. Any ideas?
You must also set same bit in the P5SEL register to change the output
of the pin from a standard I/O to its "alternate function", i.e.
output of the MCLK.
Chris
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