Hi all,
I need 2 PWM output signals and the second must have a programmable
delay. The first signal can be generated by timerA -ok.
For the second one a additional timer is needed wich can started from
TimerA but the watchdog is to slow and a high interrupt frequency would
be. Has anyone a solution? I think that is a common problem.
Thanks a lot.
Ulrich.
2 PWM output signal on 2013
Started by ●August 3, 2007
Reply by ●August 3, 20072007-08-03
Which MSP430 chip are you using? What do you mean by "programmable
delay"? Do you mean duty cycle? Modulation frequency? Phase delay?
If the chip has two Timers, you can generate two independent PWM outputs.
If the chip has only one Timer with three (or more) CCR, you can
generate two PWM with same frequency but different duty cycles. (Also,
one of the edges of one PWM must coincide with one of the edges of the
other PWM.)
--- In m..., "ulrich_probst" wrote:
>
> Hi all,
> I need 2 PWM output signals and the second must have a programmable
> delay. The first signal can be generated by timerA -ok.
> For the second one a additional timer is needed wich can started from
> TimerA but the watchdog is to slow and a high interrupt frequency would
> be. Has anyone a solution? I think that is a common problem.
> Thanks a lot.
> Ulrich.
>
delay"? Do you mean duty cycle? Modulation frequency? Phase delay?
If the chip has two Timers, you can generate two independent PWM outputs.
If the chip has only one Timer with three (or more) CCR, you can
generate two PWM with same frequency but different duty cycles. (Also,
one of the edges of one PWM must coincide with one of the edges of the
other PWM.)
--- In m..., "ulrich_probst" wrote:
>
> Hi all,
> I need 2 PWM output signals and the second must have a programmable
> delay. The first signal can be generated by timerA -ok.
> For the second one a additional timer is needed wich can started from
> TimerA but the watchdog is to slow and a high interrupt frequency would
> be. Has anyone a solution? I think that is a common problem.
> Thanks a lot.
> Ulrich.
>
Reply by ●August 6, 20072007-08-06
Thanks for your answer. I use the MSP430x2013. This uC has only the
timer A and the Watchdog. With Timer A one can generate 1 PWM Signal.
CCR0 for frequency and CCR1 for pulse width is used. The MSP430x2013
has no CCR2 and so a start of generating the second pulse is not
possible. The delay time of output signal#2 shall be programmable in
respect to #1 and to set in the range 0...T. T=periode of output
signal1.
One possebility would be to start 2 SW-Counter triggered by a PWM-
signal from Timer A. Each SW-Counter counts the ticks from Watchdog
counter. The drawback is the high INT burden and the resolution of
the watchdog INT frequncy is pretty coarse.
Ulrich.
--- In m..., "old_cow_yellow"
wrote:
>
> Which MSP430 chip are you using? What do you mean by "programmable
> delay"? Do you mean duty cycle? Modulation frequency? Phase delay?
>
> If the chip has two Timers, you can generate two independent PWM
outputs.
>
> If the chip has only one Timer with three (or more) CCR, you can
> generate two PWM with same frequency but different duty cycles.
(Also,
> one of the edges of one PWM must coincide with one of the edges of
the
> other PWM.)
>
> --- In m..., "ulrich_probst"
wrote:
>
> >
> > Hi all,
> > I need 2 PWM output signals and the second must have a
programmable
> > delay. The first signal can be generated by timerA -ok.
> > For the second one a additional timer is needed wich can started
from
> > TimerA but the watchdog is to slow and a high interrupt frequency
would
> > be. Has anyone a solution? I think that is a common problem.
> > Thanks a lot.
> > Ulrich.
>
timer A and the Watchdog. With Timer A one can generate 1 PWM Signal.
CCR0 for frequency and CCR1 for pulse width is used. The MSP430x2013
has no CCR2 and so a start of generating the second pulse is not
possible. The delay time of output signal#2 shall be programmable in
respect to #1 and to set in the range 0...T. T=periode of output
signal1.
One possebility would be to start 2 SW-Counter triggered by a PWM-
signal from Timer A. Each SW-Counter counts the ticks from Watchdog
counter. The drawback is the high INT burden and the resolution of
the watchdog INT frequncy is pretty coarse.
Ulrich.
--- In m..., "old_cow_yellow"
wrote:
>
> Which MSP430 chip are you using? What do you mean by "programmable
> delay"? Do you mean duty cycle? Modulation frequency? Phase delay?
>
> If the chip has two Timers, you can generate two independent PWM
outputs.
>
> If the chip has only one Timer with three (or more) CCR, you can
> generate two PWM with same frequency but different duty cycles.
(Also,
> one of the edges of one PWM must coincide with one of the edges of
the
> other PWM.)
>
> --- In m..., "ulrich_probst"
wrote:
>
> >
> > Hi all,
> > I need 2 PWM output signals and the second must have a
programmable
> > delay. The first signal can be generated by timerA -ok.
> > For the second one a additional timer is needed wich can started
from
> > TimerA but the watchdog is to slow and a high interrupt frequency
would
> > be. Has anyone a solution? I think that is a common problem.
> > Thanks a lot.
> > Ulrich.
>
Reply by ●August 6, 20072007-08-06
--- In m..., "ulrich_probst" wrote:
>
> Hi all,
> I need 2 PWM output signals and the second must have a programmable
> delay. The first signal can be generated by timerA -ok.
> For the second one a additional timer is needed wich can started from
> TimerA but the watchdog is to slow and a high interrupt frequency would
> be. Has anyone a solution? I think that is a common problem.
> Thanks a lot.
> Ulrich.
>
Hi Ulrich,
I have to do something similar because I ran out of CC units. I am
not really sure of your application but you can manipulate CCR0 to
generate one output and CCR1 to generate the other output. Software
load is a bit higher than if you had another CCR but it should work.
You can program CCR0 to generate your frequency by programming two
numbers and using two OUTMODs. Run the timer in continuous mode.
Start it out by using the "RESET" OUTMOD for CCR0. When you
initialize everything, before you turn on the timer, put something
like 1/2 your frequency into CCR0. Enable interrupts. When you get an
interrupt from it resetting OUT, you can then add 1/2 your frequency
to CCR0 and change the OUTMOD to "SET". You can then add your second
pulse offset to the new value in CCR0 (where it will set OUT) and put
that in CCR1. Set CCR1 to OUTMOD "SET". When you get the next
interrupt on CCR0 from the "SET" command, add 1/2 frequency again and
change back to "RESET" command. When you get an interrupt from CCR1
after it sets OUT, add your pulse width to CCR1 and change the OUTMOD
to "RESET". This is a little complicated but it, or a slight
variation, should work.
>
> Hi all,
> I need 2 PWM output signals and the second must have a programmable
> delay. The first signal can be generated by timerA -ok.
> For the second one a additional timer is needed wich can started from
> TimerA but the watchdog is to slow and a high interrupt frequency would
> be. Has anyone a solution? I think that is a common problem.
> Thanks a lot.
> Ulrich.
>
Hi Ulrich,
I have to do something similar because I ran out of CC units. I am
not really sure of your application but you can manipulate CCR0 to
generate one output and CCR1 to generate the other output. Software
load is a bit higher than if you had another CCR but it should work.
You can program CCR0 to generate your frequency by programming two
numbers and using two OUTMODs. Run the timer in continuous mode.
Start it out by using the "RESET" OUTMOD for CCR0. When you
initialize everything, before you turn on the timer, put something
like 1/2 your frequency into CCR0. Enable interrupts. When you get an
interrupt from it resetting OUT, you can then add 1/2 your frequency
to CCR0 and change the OUTMOD to "SET". You can then add your second
pulse offset to the new value in CCR0 (where it will set OUT) and put
that in CCR1. Set CCR1 to OUTMOD "SET". When you get the next
interrupt on CCR0 from the "SET" command, add 1/2 frequency again and
change back to "RESET" command. When you get an interrupt from CCR1
after it sets OUT, add your pulse width to CCR1 and change the OUTMOD
to "RESET". This is a little complicated but it, or a slight
variation, should work.
Reply by ●August 6, 20072007-08-06
You are using Timer_A2 in a MSP430F2013 to generate one PWM output.
Let us review this part first (please be patient).
(a) Set up CCR0 to a value N. (N must be much bigger than 0.)
(b) Set up CCR1 to a value M. (M must be between 0 and N inclusive).
(c) Set up CCTL1:OUTMODx bits to 010, 011, 110, or 111.
(d) Set up TACTL to count at frequency F and count up to CCR0 (MCx
bits = 01).
This will produce a PWM waveform with frequency F/(N+1) and a duty
cycle of either M/(N+1) or (N+1-M)/(N+1) depending on the
CCTL1:OUTMODx bits.
If those bits are 010 or 011, the waveform is at Vcc for M counts
followed by at Gnd for (N+1-M) counts.
If those bits are 110 or 111, the waveform is at Gnd for M counts
followed by at Vcc for (N+1-M) counts.
Both the frequency and duty cycle of this PWM are "programmable"
because the CPU can change F, N, M, and CCTL1:OUTMODx bits. But other
than that, Timer_A2 will generate this PWM waveform all by itself and
does not need the CPU to do anything.
Timer_A2 also has other capabilities that are not used by the
aforementioned scheme.
(1) If you set up CCTL0:OUTMODx to 001, 100, or 101, it will Set,
Toggle, or Reset (respectively) another output signal when TAR counts
to N
(2) It can generate an interrupt when TAR counts to N.
(3) It can generate an interrupt when TAR counts to M.
These capabilities can help you to generate another PWM output. For
example, you can use (1) to Set the output to Vcc, use (2) or (3) to
generate an interrupt to Reset that output to Gnd. Inside that
interrupt routine, you can either rely on the number of MCLK cycles to
execute the code, or poll TAR to decide when to Reset the output.
Doing it this way, the frequency is the same as the other PWM, namely
F/(N+1). The duty cycle is "programmable" independent to that of the
other PWM.
If you can tell me the ballpark value of F-N-M of the first PWM and
the requirement of the second PWM, I may be able to be more specific too.
--- In m..., "ulrich_probst" wrote:
>
> Thanks for your answer. I use the MSP430x2013. This uC has only the
> timer A and the Watchdog. With Timer A one can generate 1 PWM Signal.
> CCR0 for frequency and CCR1 for pulse width is used. The MSP430x2013
> has no CCR2 and so a start of generating the second pulse is not
> possible. The delay time of output signal#2 shall be programmable in
> respect to #1 and to set in the range 0...T. T=periode of output
> signal1.
> One possebility would be to start 2 SW-Counter triggered by a PWM-
> signal from Timer A. Each SW-Counter counts the ticks from Watchdog
> counter. The drawback is the high INT burden and the resolution of
> the watchdog INT frequncy is pretty coarse.
> Ulrich.
>
> --- In m..., "old_cow_yellow"
> wrote:
> >
> > Which MSP430 chip are you using? What do you mean by "programmable
> > delay"? Do you mean duty cycle? Modulation frequency? Phase delay?
> >
> > If the chip has two Timers, you can generate two independent PWM
> outputs.
> >
> > If the chip has only one Timer with three (or more) CCR, you can
> > generate two PWM with same frequency but different duty cycles.
> (Also,
> > one of the edges of one PWM must coincide with one of the edges of
> the
> > other PWM.)
> >
> > --- In m..., "ulrich_probst"
> wrote:
> >
> > >
> > > Hi all,
> > > I need 2 PWM output signals and the second must have a
> programmable
> > > delay. The first signal can be generated by timerA -ok.
> > > For the second one a additional timer is needed wich can started
> from
> > > TimerA but the watchdog is to slow and a high interrupt frequency
> would
> > > be. Has anyone a solution? I think that is a common problem.
> > > Thanks a lot.
> > > Ulrich.
> > >
>
Let us review this part first (please be patient).
(a) Set up CCR0 to a value N. (N must be much bigger than 0.)
(b) Set up CCR1 to a value M. (M must be between 0 and N inclusive).
(c) Set up CCTL1:OUTMODx bits to 010, 011, 110, or 111.
(d) Set up TACTL to count at frequency F and count up to CCR0 (MCx
bits = 01).
This will produce a PWM waveform with frequency F/(N+1) and a duty
cycle of either M/(N+1) or (N+1-M)/(N+1) depending on the
CCTL1:OUTMODx bits.
If those bits are 010 or 011, the waveform is at Vcc for M counts
followed by at Gnd for (N+1-M) counts.
If those bits are 110 or 111, the waveform is at Gnd for M counts
followed by at Vcc for (N+1-M) counts.
Both the frequency and duty cycle of this PWM are "programmable"
because the CPU can change F, N, M, and CCTL1:OUTMODx bits. But other
than that, Timer_A2 will generate this PWM waveform all by itself and
does not need the CPU to do anything.
Timer_A2 also has other capabilities that are not used by the
aforementioned scheme.
(1) If you set up CCTL0:OUTMODx to 001, 100, or 101, it will Set,
Toggle, or Reset (respectively) another output signal when TAR counts
to N
(2) It can generate an interrupt when TAR counts to N.
(3) It can generate an interrupt when TAR counts to M.
These capabilities can help you to generate another PWM output. For
example, you can use (1) to Set the output to Vcc, use (2) or (3) to
generate an interrupt to Reset that output to Gnd. Inside that
interrupt routine, you can either rely on the number of MCLK cycles to
execute the code, or poll TAR to decide when to Reset the output.
Doing it this way, the frequency is the same as the other PWM, namely
F/(N+1). The duty cycle is "programmable" independent to that of the
other PWM.
If you can tell me the ballpark value of F-N-M of the first PWM and
the requirement of the second PWM, I may be able to be more specific too.
--- In m..., "ulrich_probst" wrote:
>
> Thanks for your answer. I use the MSP430x2013. This uC has only the
> timer A and the Watchdog. With Timer A one can generate 1 PWM Signal.
> CCR0 for frequency and CCR1 for pulse width is used. The MSP430x2013
> has no CCR2 and so a start of generating the second pulse is not
> possible. The delay time of output signal#2 shall be programmable in
> respect to #1 and to set in the range 0...T. T=periode of output
> signal1.
> One possebility would be to start 2 SW-Counter triggered by a PWM-
> signal from Timer A. Each SW-Counter counts the ticks from Watchdog
> counter. The drawback is the high INT burden and the resolution of
> the watchdog INT frequncy is pretty coarse.
> Ulrich.
>
> --- In m..., "old_cow_yellow"
> wrote:
> >
> > Which MSP430 chip are you using? What do you mean by "programmable
> > delay"? Do you mean duty cycle? Modulation frequency? Phase delay?
> >
> > If the chip has two Timers, you can generate two independent PWM
> outputs.
> >
> > If the chip has only one Timer with three (or more) CCR, you can
> > generate two PWM with same frequency but different duty cycles.
> (Also,
> > one of the edges of one PWM must coincide with one of the edges of
> the
> > other PWM.)
> >
> > --- In m..., "ulrich_probst"
> wrote:
> >
> > >
> > > Hi all,
> > > I need 2 PWM output signals and the second must have a
> programmable
> > > delay. The first signal can be generated by timerA -ok.
> > > For the second one a additional timer is needed wich can started
> from
> > > TimerA but the watchdog is to slow and a high interrupt frequency
> would
> > > be. Has anyone a solution? I think that is a common problem.
> > > Thanks a lot.
> > > Ulrich.
> > >
>
Reply by ●August 9, 20072007-08-09
Hello old_cow_yellow,
thanks you very much indeed. If I have right understood you will
generate the first PWM signal with an output function -o.k. The 2nd
one shall be generated in an Timer-ISR,which is started each time
when TAR = 0.When TAR has reached the delay value D the PWM2 output
is set and when TAR = D + pulse width output PWM2 will be reset and
the ISR is finished. In the ISR I must poll the TAR.
Can I poll the TAR at all or must I use the capture function?
For the clock I could use the DCO 1 MHz. The PWM-Period P should be
382ms, the duty cycle 0.66 and the delay D of PWM2 = 1/6*P= 64ms.
Thanks in advance.
Ulrich.
--- In m..., "old_cow_yellow"
wrote:
>
> You are using Timer_A2 in a MSP430F2013 to generate one PWM output.
> Let us review this part first (please be patient).
>
> (a) Set up CCR0 to a value N. (N must be much bigger than 0.)
> (b) Set up CCR1 to a value M. (M must be between 0 and N inclusive).
> (c) Set up CCTL1:OUTMODx bits to 010, 011, 110, or 111.
> (d) Set up TACTL to count at frequency F and count up to CCR0 (MCx
> bits = 01).
>
> This will produce a PWM waveform with frequency F/(N+1) and a duty
> cycle of either M/(N+1) or (N+1-M)/(N+1) depending on the
> CCTL1:OUTMODx bits.
>
> If those bits are 010 or 011, the waveform is at Vcc for M counts
> followed by at Gnd for (N+1-M) counts.
>
> If those bits are 110 or 111, the waveform is at Gnd for M counts
> followed by at Vcc for (N+1-M) counts.
>
> Both the frequency and duty cycle of this PWM are "programmable"
> because the CPU can change F, N, M, and CCTL1:OUTMODx bits. But
other
> than that, Timer_A2 will generate this PWM waveform all by itself
and
> does not need the CPU to do anything.
>
> Timer_A2 also has other capabilities that are not used by the
> aforementioned scheme.
>
> (1) If you set up CCTL0:OUTMODx to 001, 100, or 101, it will Set,
> Toggle, or Reset (respectively) another output signal when TAR
counts
> to N
> (2) It can generate an interrupt when TAR counts to N.
> (3) It can generate an interrupt when TAR counts to M.
>
> These capabilities can help you to generate another PWM output. For
> example, you can use (1) to Set the output to Vcc, use (2) or (3) to
> generate an interrupt to Reset that output to Gnd. Inside that
> interrupt routine, you can either rely on the number of MCLK cycles
to
> execute the code, or poll TAR to decide when to Reset the output.
>
> Doing it this way, the frequency is the same as the other PWM,
namely
> F/(N+1). The duty cycle is "programmable" independent to that of the
> other PWM.
>
> If you can tell me the ballpark value of F-N-M of the first PWM and
> the requirement of the second PWM, I may be able to be more
specific too.
>
> --- In m..., "ulrich_probst"
wrote:
> >
> > Thanks for your answer. I use the MSP430x2013. This uC has only
the
> > timer A and the Watchdog. With Timer A one can generate 1 PWM
Signal.
> > CCR0 for frequency and CCR1 for pulse width is used. The
MSP430x2013
> > has no CCR2 and so a start of generating the second pulse is not
> > possible. The delay time of output signal#2 shall be
programmable in
> > respect to #1 and to set in the range 0...T. T=periode of output
> > signal1.
> > One possebility would be to start 2 SW-Counter triggered by a PWM-
> > signal from Timer A. Each SW-Counter counts the ticks from
Watchdog
> > counter. The drawback is the high INT burden and the resolution
of
> > the watchdog INT frequncy is pretty coarse.
> > Ulrich.
> >
> > --- In m..., "old_cow_yellow"
> > wrote:
> > >
> > > Which MSP430 chip are you using? What do you mean
by "programmable
> > > delay"? Do you mean duty cycle? Modulation frequency? Phase
delay?
> > >
> > > If the chip has two Timers, you can generate two independent
PWM
> > outputs.
> > >
> > > If the chip has only one Timer with three (or more) CCR, you can
> > > generate two PWM with same frequency but different duty cycles.
> > (Also,
> > > one of the edges of one PWM must coincide with one of the edges
of
> > the
> > > other PWM.)
> > >
> > > --- In m..., "ulrich_probst"
> > wrote:
> > >
> > > >
> > > > Hi all,
> > > > I need 2 PWM output signals and the second must have a
> > programmable
> > > > delay. The first signal can be generated by timerA -ok.
> > > > For the second one a additional timer is needed wich can
started
> > from
> > > > TimerA but the watchdog is to slow and a high interrupt
frequency
> > would
> > > > be. Has anyone a solution? I think that is a common problem.
> > > > Thanks a lot.
> > > > Ulrich.
> > > >
> > >
>
thanks you very much indeed. If I have right understood you will
generate the first PWM signal with an output function -o.k. The 2nd
one shall be generated in an Timer-ISR,which is started each time
when TAR = 0.When TAR has reached the delay value D the PWM2 output
is set and when TAR = D + pulse width output PWM2 will be reset and
the ISR is finished. In the ISR I must poll the TAR.
Can I poll the TAR at all or must I use the capture function?
For the clock I could use the DCO 1 MHz. The PWM-Period P should be
382ms, the duty cycle 0.66 and the delay D of PWM2 = 1/6*P= 64ms.
Thanks in advance.
Ulrich.
--- In m..., "old_cow_yellow"
wrote:
>
> You are using Timer_A2 in a MSP430F2013 to generate one PWM output.
> Let us review this part first (please be patient).
>
> (a) Set up CCR0 to a value N. (N must be much bigger than 0.)
> (b) Set up CCR1 to a value M. (M must be between 0 and N inclusive).
> (c) Set up CCTL1:OUTMODx bits to 010, 011, 110, or 111.
> (d) Set up TACTL to count at frequency F and count up to CCR0 (MCx
> bits = 01).
>
> This will produce a PWM waveform with frequency F/(N+1) and a duty
> cycle of either M/(N+1) or (N+1-M)/(N+1) depending on the
> CCTL1:OUTMODx bits.
>
> If those bits are 010 or 011, the waveform is at Vcc for M counts
> followed by at Gnd for (N+1-M) counts.
>
> If those bits are 110 or 111, the waveform is at Gnd for M counts
> followed by at Vcc for (N+1-M) counts.
>
> Both the frequency and duty cycle of this PWM are "programmable"
> because the CPU can change F, N, M, and CCTL1:OUTMODx bits. But
other
> than that, Timer_A2 will generate this PWM waveform all by itself
and
> does not need the CPU to do anything.
>
> Timer_A2 also has other capabilities that are not used by the
> aforementioned scheme.
>
> (1) If you set up CCTL0:OUTMODx to 001, 100, or 101, it will Set,
> Toggle, or Reset (respectively) another output signal when TAR
counts
> to N
> (2) It can generate an interrupt when TAR counts to N.
> (3) It can generate an interrupt when TAR counts to M.
>
> These capabilities can help you to generate another PWM output. For
> example, you can use (1) to Set the output to Vcc, use (2) or (3) to
> generate an interrupt to Reset that output to Gnd. Inside that
> interrupt routine, you can either rely on the number of MCLK cycles
to
> execute the code, or poll TAR to decide when to Reset the output.
>
> Doing it this way, the frequency is the same as the other PWM,
namely
> F/(N+1). The duty cycle is "programmable" independent to that of the
> other PWM.
>
> If you can tell me the ballpark value of F-N-M of the first PWM and
> the requirement of the second PWM, I may be able to be more
specific too.
>
> --- In m..., "ulrich_probst"
wrote:
> >
> > Thanks for your answer. I use the MSP430x2013. This uC has only
the
> > timer A and the Watchdog. With Timer A one can generate 1 PWM
Signal.
> > CCR0 for frequency and CCR1 for pulse width is used. The
MSP430x2013
> > has no CCR2 and so a start of generating the second pulse is not
> > possible. The delay time of output signal#2 shall be
programmable in
> > respect to #1 and to set in the range 0...T. T=periode of output
> > signal1.
> > One possebility would be to start 2 SW-Counter triggered by a PWM-
> > signal from Timer A. Each SW-Counter counts the ticks from
Watchdog
> > counter. The drawback is the high INT burden and the resolution
of
> > the watchdog INT frequncy is pretty coarse.
> > Ulrich.
> >
> > --- In m..., "old_cow_yellow"
> > wrote:
> > >
> > > Which MSP430 chip are you using? What do you mean
by "programmable
> > > delay"? Do you mean duty cycle? Modulation frequency? Phase
delay?
> > >
> > > If the chip has two Timers, you can generate two independent
PWM
> > outputs.
> > >
> > > If the chip has only one Timer with three (or more) CCR, you can
> > > generate two PWM with same frequency but different duty cycles.
> > (Also,
> > > one of the edges of one PWM must coincide with one of the edges
of
> > the
> > > other PWM.)
> > >
> > > --- In m..., "ulrich_probst"
> > wrote:
> > >
> > > >
> > > > Hi all,
> > > > I need 2 PWM output signals and the second must have a
> > programmable
> > > > delay. The first signal can be generated by timerA -ok.
> > > > For the second one a additional timer is needed wich can
started
> > from
> > > > TimerA but the watchdog is to slow and a high interrupt
frequency
> > would
> > > > be. Has anyone a solution? I think that is a common problem.
> > > > Thanks a lot.
> > > > Ulrich.
> > > >
> > >
>
Reply by ●August 11, 20072007-08-11
Hello Ulrich,
You understood me correctly. But you cannot use capture mode because
that will destroy CCRn register.
If the period is 384ms, counting at 1MHz is too fast. This is because
you are using a 16-bit Timer. 1MHz/8 = 125kHz will work fine.
Using the above method will make the CPU very busy checking TAR.
The following code uses a totally different method. CPU is in LPM0 most
of the time and the interrupt service routines take very little time to
execute.
#include "msp430.h"
;-------
T EQU 48000 ;Period of PWM_0 and PWM_1 => 384 ms @ 125
kHz
W0 EQU T*2/3 ;Width of PWM_0
D EQU T/6 ;Delay of PWM_1 relative to PWM_0
W1 EQU T/4 ;Width of PWM_1
;-------
RSEG INTVEC
ORG TIMERA1_VECTOR
DC16 isr1
ORG TIMERA0_VECTOR
DC16 isr0
;-------
RSEG RESET
DC16 main
;-------
RSEG CSTACK
;-------
RSEG CODE
main: MOV #SFE(CSTACK), SP
MOV.W #WDTPW+WDTHOLD,&WDTCTL
MOV.B &CALDCO_1MHZ,&DCOCTL
MOV.B &CALBC1_1MHZ,&BCSCTL1 ;MCLK = SMCLK = 1 MHz
BIS.B #BIT5|BIT6|BIT7,&P1DIR
BIS.B #BIT5|BIT6,&P1SEL
MOV.W #123,&CCR0
MOV.W #123+D,&CCR1
MOV.W #OUTMOD_1|CCIE,&CCTL0
MOV.W #OUTMOD_1|CCIE,&CCTL1
MOV.W #TASSEL_2|ID_3|MC_2|TACLR,&TACTL
BIS.W #CPUOFF|GIE,SR ;LPM 0
Y: jmp y ;Safty net
;-------
isr0: BIT.W #OUTMOD2,&CCTL0
JZ x0
BIC.W #OUTMOD2,&CCTL0
ADD.W #T-W0,&CCR0
RETI
x0: BIS.W #OUTMOD2,&CCTL0
ADD.W #W0,&CCR0
RETI
;-------
isr1: BIT.W #0,&TAIV
BIT.W #OUTMOD2,&CCTL1
JZ x1
BIC.W #OUTMOD2,&CCTL1
ADD.W #T-W1,&CCR1
RETI
x1: BIS.W #OUTMOD2,&CCTL1
ADD.W #W1,&CCR1
RETI
;-------
END
--- In m..., "ulrich_probst"
wrote:
>
> Hello old_cow_yellow,
> thanks you very much indeed. If I have right understood you will
> generate the first PWM signal with an output function -o.k. The 2nd
> one shall be generated in an Timer-ISR,which is started each time
> when TAR = 0.When TAR has reached the delay value D the PWM2 output
> is set and when TAR = D + pulse width output PWM2 will be reset and
> the ISR is finished. In the ISR I must poll the TAR.
> Can I poll the TAR at all or must I use the capture function?
> For the clock I could use the DCO 1 MHz. The PWM-Period P should be
> 382ms, the duty cycle 0.66 and the delay D of PWM2 = 1/6*P= 64ms.
> Thanks in advance.
> Ulrich.
>
> --- In m..., "old_cow_yellow" old_cow_yellow@
> wrote:
> >
> > You are using Timer_A2 in a MSP430F2013 to generate one PWM output.
> > Let us review this part first (please be patient).
> >
> > (a) Set up CCR0 to a value N. (N must be much bigger than 0.)
> > (b) Set up CCR1 to a value M. (M must be between 0 and N inclusive).
> > (c) Set up CCTL1:OUTMODx bits to 010, 011, 110, or 111.
> > (d) Set up TACTL to count at frequency F and count up to CCR0 (MCx
> > bits = 01).
> >
> > This will produce a PWM waveform with frequency F/(N+1) and a duty
> > cycle of either M/(N+1) or (N+1-M)/(N+1) depending on the
> > CCTL1:OUTMODx bits.
> >
> > If those bits are 010 or 011, the waveform is at Vcc for M counts
> > followed by at Gnd for (N+1-M) counts.
> >
> > If those bits are 110 or 111, the waveform is at Gnd for M counts
> > followed by at Vcc for (N+1-M) counts.
> >
> > Both the frequency and duty cycle of this PWM are "programmable"
> > because the CPU can change F, N, M, and CCTL1:OUTMODx bits. But
> other
> > than that, Timer_A2 will generate this PWM waveform all by itself
> and
> > does not need the CPU to do anything.
> >
> > Timer_A2 also has other capabilities that are not used by the
> > aforementioned scheme.
> >
> > (1) If you set up CCTL0:OUTMODx to 001, 100, or 101, it will Set,
> > Toggle, or Reset (respectively) another output signal when TAR
> counts
> > to N
> > (2) It can generate an interrupt when TAR counts to N.
> > (3) It can generate an interrupt when TAR counts to M.
> >
> > These capabilities can help you to generate another PWM output. For
> > example, you can use (1) to Set the output to Vcc, use (2) or (3) to
> > generate an interrupt to Reset that output to Gnd. Inside that
> > interrupt routine, you can either rely on the number of MCLK cycles
> to
> > execute the code, or poll TAR to decide when to Reset the output.
> >
> > Doing it this way, the frequency is the same as the other PWM,
> namely
> > F/(N+1). The duty cycle is "programmable" independent to that of the
> > other PWM.
> >
> > If you can tell me the ballpark value of F-N-M of the first PWM and
> > the requirement of the second PWM, I may be able to be more
> specific too.
> >
> > --- In m..., "ulrich_probst"
> wrote:
> > >
> > > Thanks for your answer. I use the MSP430x2013. This uC has only
> the
> > > timer A and the Watchdog. With Timer A one can generate 1 PWM
> Signal.
> > > CCR0 for frequency and CCR1 for pulse width is used. The
> MSP430x2013
> > > has no CCR2 and so a start of generating the second pulse is not
> > > possible. The delay time of output signal#2 shall be
> programmable in
> > > respect to #1 and to set in the range 0...T. T=periode of output
> > > signal1.
> > > One possebility would be to start 2 SW-Counter triggered by a PWM-
> > > signal from Timer A. Each SW-Counter counts the ticks from
> Watchdog
> > > counter. The drawback is the high INT burden and the resolution
> of
> > > the watchdog INT frequncy is pretty coarse.
> > > Ulrich.
> > >
> > > --- In m..., "old_cow_yellow"
> > > wrote:
> > > >
> > > > Which MSP430 chip are you using? What do you mean
> by "programmable
> > > > delay"? Do you mean duty cycle? Modulation frequency? Phase
> delay?
> > > >
> > > > If the chip has two Timers, you can generate two independent
> PWM
> > > outputs.
> > > >
> > > > If the chip has only one Timer with three (or more) CCR, you can
> > > > generate two PWM with same frequency but different duty cycles.
> > > (Also,
> > > > one of the edges of one PWM must coincide with one of the edges
> of
> > > the
> > > > other PWM.)
> > > >
> > > > --- In m..., "ulrich_probst"
> > > wrote:
> > > >
> > > > >
> > > > > Hi all,
> > > > > I need 2 PWM output signals and the second must have a
> > > programmable
> > > > > delay. The first signal can be generated by timerA -ok.
> > > > > For the second one a additional timer is needed wich can
> started
> > > from
> > > > > TimerA but the watchdog is to slow and a high interrupt
> frequency
> > > would
> > > > > be. Has anyone a solution? I think that is a common problem.
> > > > > Thanks a lot.
> > > > > Ulrich.
> > > > >
> > > >
> > >
>
You understood me correctly. But you cannot use capture mode because
that will destroy CCRn register.
If the period is 384ms, counting at 1MHz is too fast. This is because
you are using a 16-bit Timer. 1MHz/8 = 125kHz will work fine.
Using the above method will make the CPU very busy checking TAR.
The following code uses a totally different method. CPU is in LPM0 most
of the time and the interrupt service routines take very little time to
execute.
#include "msp430.h"
;-------
T EQU 48000 ;Period of PWM_0 and PWM_1 => 384 ms @ 125
kHz
W0 EQU T*2/3 ;Width of PWM_0
D EQU T/6 ;Delay of PWM_1 relative to PWM_0
W1 EQU T/4 ;Width of PWM_1
;-------
RSEG INTVEC
ORG TIMERA1_VECTOR
DC16 isr1
ORG TIMERA0_VECTOR
DC16 isr0
;-------
RSEG RESET
DC16 main
;-------
RSEG CSTACK
;-------
RSEG CODE
main: MOV #SFE(CSTACK), SP
MOV.W #WDTPW+WDTHOLD,&WDTCTL
MOV.B &CALDCO_1MHZ,&DCOCTL
MOV.B &CALBC1_1MHZ,&BCSCTL1 ;MCLK = SMCLK = 1 MHz
BIS.B #BIT5|BIT6|BIT7,&P1DIR
BIS.B #BIT5|BIT6,&P1SEL
MOV.W #123,&CCR0
MOV.W #123+D,&CCR1
MOV.W #OUTMOD_1|CCIE,&CCTL0
MOV.W #OUTMOD_1|CCIE,&CCTL1
MOV.W #TASSEL_2|ID_3|MC_2|TACLR,&TACTL
BIS.W #CPUOFF|GIE,SR ;LPM 0
Y: jmp y ;Safty net
;-------
isr0: BIT.W #OUTMOD2,&CCTL0
JZ x0
BIC.W #OUTMOD2,&CCTL0
ADD.W #T-W0,&CCR0
RETI
x0: BIS.W #OUTMOD2,&CCTL0
ADD.W #W0,&CCR0
RETI
;-------
isr1: BIT.W #0,&TAIV
BIT.W #OUTMOD2,&CCTL1
JZ x1
BIC.W #OUTMOD2,&CCTL1
ADD.W #T-W1,&CCR1
RETI
x1: BIS.W #OUTMOD2,&CCTL1
ADD.W #W1,&CCR1
RETI
;-------
END
--- In m..., "ulrich_probst"
wrote:
>
> Hello old_cow_yellow,
> thanks you very much indeed. If I have right understood you will
> generate the first PWM signal with an output function -o.k. The 2nd
> one shall be generated in an Timer-ISR,which is started each time
> when TAR = 0.When TAR has reached the delay value D the PWM2 output
> is set and when TAR = D + pulse width output PWM2 will be reset and
> the ISR is finished. In the ISR I must poll the TAR.
> Can I poll the TAR at all or must I use the capture function?
> For the clock I could use the DCO 1 MHz. The PWM-Period P should be
> 382ms, the duty cycle 0.66 and the delay D of PWM2 = 1/6*P= 64ms.
> Thanks in advance.
> Ulrich.
>
> --- In m..., "old_cow_yellow" old_cow_yellow@
> wrote:
> >
> > You are using Timer_A2 in a MSP430F2013 to generate one PWM output.
> > Let us review this part first (please be patient).
> >
> > (a) Set up CCR0 to a value N. (N must be much bigger than 0.)
> > (b) Set up CCR1 to a value M. (M must be between 0 and N inclusive).
> > (c) Set up CCTL1:OUTMODx bits to 010, 011, 110, or 111.
> > (d) Set up TACTL to count at frequency F and count up to CCR0 (MCx
> > bits = 01).
> >
> > This will produce a PWM waveform with frequency F/(N+1) and a duty
> > cycle of either M/(N+1) or (N+1-M)/(N+1) depending on the
> > CCTL1:OUTMODx bits.
> >
> > If those bits are 010 or 011, the waveform is at Vcc for M counts
> > followed by at Gnd for (N+1-M) counts.
> >
> > If those bits are 110 or 111, the waveform is at Gnd for M counts
> > followed by at Vcc for (N+1-M) counts.
> >
> > Both the frequency and duty cycle of this PWM are "programmable"
> > because the CPU can change F, N, M, and CCTL1:OUTMODx bits. But
> other
> > than that, Timer_A2 will generate this PWM waveform all by itself
> and
> > does not need the CPU to do anything.
> >
> > Timer_A2 also has other capabilities that are not used by the
> > aforementioned scheme.
> >
> > (1) If you set up CCTL0:OUTMODx to 001, 100, or 101, it will Set,
> > Toggle, or Reset (respectively) another output signal when TAR
> counts
> > to N
> > (2) It can generate an interrupt when TAR counts to N.
> > (3) It can generate an interrupt when TAR counts to M.
> >
> > These capabilities can help you to generate another PWM output. For
> > example, you can use (1) to Set the output to Vcc, use (2) or (3) to
> > generate an interrupt to Reset that output to Gnd. Inside that
> > interrupt routine, you can either rely on the number of MCLK cycles
> to
> > execute the code, or poll TAR to decide when to Reset the output.
> >
> > Doing it this way, the frequency is the same as the other PWM,
> namely
> > F/(N+1). The duty cycle is "programmable" independent to that of the
> > other PWM.
> >
> > If you can tell me the ballpark value of F-N-M of the first PWM and
> > the requirement of the second PWM, I may be able to be more
> specific too.
> >
> > --- In m..., "ulrich_probst"
> wrote:
> > >
> > > Thanks for your answer. I use the MSP430x2013. This uC has only
> the
> > > timer A and the Watchdog. With Timer A one can generate 1 PWM
> Signal.
> > > CCR0 for frequency and CCR1 for pulse width is used. The
> MSP430x2013
> > > has no CCR2 and so a start of generating the second pulse is not
> > > possible. The delay time of output signal#2 shall be
> programmable in
> > > respect to #1 and to set in the range 0...T. T=periode of output
> > > signal1.
> > > One possebility would be to start 2 SW-Counter triggered by a PWM-
> > > signal from Timer A. Each SW-Counter counts the ticks from
> Watchdog
> > > counter. The drawback is the high INT burden and the resolution
> of
> > > the watchdog INT frequncy is pretty coarse.
> > > Ulrich.
> > >
> > > --- In m..., "old_cow_yellow"
> > > wrote:
> > > >
> > > > Which MSP430 chip are you using? What do you mean
> by "programmable
> > > > delay"? Do you mean duty cycle? Modulation frequency? Phase
> delay?
> > > >
> > > > If the chip has two Timers, you can generate two independent
> PWM
> > > outputs.
> > > >
> > > > If the chip has only one Timer with three (or more) CCR, you can
> > > > generate two PWM with same frequency but different duty cycles.
> > > (Also,
> > > > one of the edges of one PWM must coincide with one of the edges
> of
> > > the
> > > > other PWM.)
> > > >
> > > > --- In m..., "ulrich_probst"
> > > wrote:
> > > >
> > > > >
> > > > > Hi all,
> > > > > I need 2 PWM output signals and the second must have a
> > > programmable
> > > > > delay. The first signal can be generated by timerA -ok.
> > > > > For the second one a additional timer is needed wich can
> started
> > > from
> > > > > TimerA but the watchdog is to slow and a high interrupt
> frequency
> > > would
> > > > > be. Has anyone a solution? I think that is a common problem.
> > > > > Thanks a lot.
> > > > > Ulrich.
> > > > >
> > > >
> > >
>
Reply by ●September 11, 20072007-09-11
Hi Robert,
thanks for your answer. The solution is fine. Single drawback is that
I have 4 INTs,2 for each pulse (and the unserviced overflow too) -
especially that 1 pulse can achieved without any INT.
--- In m..., "Robert Ritchey" wrote:
>
> --- In m..., "ulrich_probst"
wrote:
> >
> > Hi all,
> > I need 2 PWM output signals and the second must have a
programmable
> > delay. The first signal can be generated by timerA -ok.
> > For the second one a additional timer is needed wich can started
from
> > TimerA but the watchdog is to slow and a high interrupt frequency
would
> > be. Has anyone a solution? I think that is a common problem.
> > Thanks a lot.
> > Ulrich.
> >
> Hi Ulrich,
> I have to do something similar because I ran out of CC units. I am
> not really sure of your application but you can manipulate CCR0 to
> generate one output and CCR1 to generate the other output. Software
> load is a bit higher than if you had another CCR but it should
work.
> You can program CCR0 to generate your frequency by programming two
> numbers and using two OUTMODs. Run the timer in continuous mode.
> Start it out by using the "RESET" OUTMOD for CCR0. When you
> initialize everything, before you turn on the timer, put something
> like 1/2 your frequency into CCR0. Enable interrupts. When you get
an
> interrupt from it resetting OUT, you can then add 1/2 your frequency
> to CCR0 and change the OUTMOD to "SET". You can then add your
second
> pulse offset to the new value in CCR0 (where it will set OUT) and
put
> that in CCR1. Set CCR1 to OUTMOD "SET". When you get the next
> interrupt on CCR0 from the "SET" command, add 1/2 frequency again
and
> change back to "RESET" command. When you get an interrupt from CCR1
> after it sets OUT, add your pulse width to CCR1 and change the
OUTMOD
> to "RESET". This is a little complicated but it, or a slight
> variation, should work.
>
thanks for your answer. The solution is fine. Single drawback is that
I have 4 INTs,2 for each pulse (and the unserviced overflow too) -
especially that 1 pulse can achieved without any INT.
--- In m..., "Robert Ritchey" wrote:
>
> --- In m..., "ulrich_probst"
wrote:
> >
> > Hi all,
> > I need 2 PWM output signals and the second must have a
programmable
> > delay. The first signal can be generated by timerA -ok.
> > For the second one a additional timer is needed wich can started
from
> > TimerA but the watchdog is to slow and a high interrupt frequency
would
> > be. Has anyone a solution? I think that is a common problem.
> > Thanks a lot.
> > Ulrich.
> >
> Hi Ulrich,
> I have to do something similar because I ran out of CC units. I am
> not really sure of your application but you can manipulate CCR0 to
> generate one output and CCR1 to generate the other output. Software
> load is a bit higher than if you had another CCR but it should
work.
> You can program CCR0 to generate your frequency by programming two
> numbers and using two OUTMODs. Run the timer in continuous mode.
> Start it out by using the "RESET" OUTMOD for CCR0. When you
> initialize everything, before you turn on the timer, put something
> like 1/2 your frequency into CCR0. Enable interrupts. When you get
an
> interrupt from it resetting OUT, you can then add 1/2 your frequency
> to CCR0 and change the OUTMOD to "SET". You can then add your
second
> pulse offset to the new value in CCR0 (where it will set OUT) and
put
> that in CCR1. Set CCR1 to OUTMOD "SET". When you get the next
> interrupt on CCR0 from the "SET" command, add 1/2 frequency again
and
> change back to "RESET" command. When you get an interrupt from CCR1
> after it sets OUT, add your pulse width to CCR1 and change the
OUTMOD
> to "RESET". This is a little complicated but it, or a slight
> variation, should work.
>
