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MSP430F149 ADC question.

Started by Sumukh Pathare July 31, 2003
I am using MSP430F149. I would like to use the on-chip
ADC to perform ADC on a signal when an external
digital line goes from low to high. How can this be
accomplished? The datasheet says that the on-chip ADC
start-of-conversion can be controlled by:
1. ADC12SC (which is a on-chip bit settable in
software)
2. Timer_A3.Out1
3. Timer_Bx.Out0 or
4. Timer_Bx.Out1.
All these are internal signals.

There doesn't seem to be a way by which an external
event can trigger conversion, except making the
external event to cause an interrupt and inside the
ISR set the ADC12SC bit. I don't want to do that since
it introduces variable latency in doing ADC.

Is there a way to make this happen?

-Sumukh


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Beginning Microcontrollers with the MSP430

Sumukh Pathare wrote:
> I am using MSP430F149. I would like to use the
on-chip
> ADC to perform ADC on a signal when an external
> digital line goes from low to high. How can this be
> accomplished? The datasheet says that the on-chip ADC
> start-of-conversion can be controlled by:
> 1. ADC12SC (which is a on-chip bit settable in
> software)
> 2. Timer_A3.Out1
> 3. Timer_Bx.Out0 or
> 4. Timer_Bx.Out1.
> All these are internal signals.

I doubt that this will work, I've never tried it, but EQUx is set on a 
capture event, and OUTx can be configured to SET on EQUx. I assume that 
OUTx only does this in output mode, but it's worth seeing if OUTx will 
follow EQUx in capture mode. Failing that you're basically stuck.

However, unless  under a microsecond of  jitter on the conversion time 
is critical to your application the latency issue isn't a big deal. The 
variation in interrupt latency is only between 1 and 6 clock cycles, 
being the shortest and longest instruction timings respectively. The 
rest of the ISR latency is fixed. jitter is therefore just 625nsecs at 
8MHz. If this is an issue you'll need to go to an external simultaneous 
dual conversion part.

Al

> 
> There doesn't seem to be a way by which an external
> event can trigger conversion, except making the
> external event to cause an interrupt and inside the
> ISR set the ADC12SC bit. I don't want to do that since
> it introduces variable latency in doing ADC.
> 
> Is there a way to make this happen?
> 
> -Sumukh
> 
> 
> __________________________________
> 
> 
> 
> .
> 
>  
> 
> ">http://docs.yahoo.com/info/terms/ 
> 
> 
> 


I believe you can accomplish this by using the external signal 
to "clock" timerA through the TACLK input. Then set the TACCR1 
register to 1 and place it in compare mode. Also set the mode for 
CCR1 so that the "OUT" bit goes high on EQUx(something like 
TACTL1=OUT_3 and TACTL=MC_1+SSEL_0. Set CCR0 to some large number. 
The ADC will  start conversion when the external signal goes high.

Mike 

--- In msp430@msp4..., onestone <onestone@b...> wrote:
> Sumukh Pathare wrote:
> > I am using MSP430F149. I would like to use the on-chip
> > ADC to perform ADC on a signal when an external
> > digital line goes from low to high. How can this be
> > accomplished? The datasheet says that the on-chip ADC
> > start-of-conversion can be controlled by:
> > 1. ADC12SC (which is a on-chip bit settable in
> > software)
> > 2. Timer_A3.Out1
> > 3. Timer_Bx.Out0 or
> > 4. Timer_Bx.Out1.
> > All these are internal signals.
> 
> I doubt that this will work, I've never tried it, but EQUx is set 
on a 
> capture event, and OUTx can be configured to SET
on EQUx. I assume 
that 
> OUTx only does this in output mode, but it's worth
seeing if OUTx 
will 
> follow EQUx in capture mode. Failing that you're
basically stuck.
> 
> However, unless  under a microsecond of  jitter on the conversion 
time 
> is critical to your application the latency issue
isn't a big deal. 
The 
> variation in interrupt latency is only between 1
and 6 clock 
cycles, 
> being the shortest and longest instruction timings
respectively. 
The 
> rest of the ISR latency is fixed. jitter is
therefore just 625nsecs 
at 
> 8MHz. If this is an issue you'll need to go to an
external 
simultaneous 
> dual conversion part.
> 
> Al
> 
> > 
> > There doesn't seem to be a way by which an external
> > event can trigger conversion, except making the
> > external event to cause an interrupt and inside the
> > ISR set the ADC12SC bit. I don't want to do that since
> > it introduces variable latency in doing ADC.
> > 
> > Is there a way to make this happen?
> > 
> > -Sumukh
> > 
> > 
> > __________________________________
> > 
> > 
> > 
> > .
> > 
> >  
> > 
> > ">http://docs.yahoo.com/info/terms/ 
> > 
> > 
> >


Mike & Onestone,
Thanks for your suggestions. I'll try both the
suggestion in the next few days. (This project got
interrupted with a higher priority task.) I'll let you
know which option works out. 

-Sumukh

--- mjruley <mjriley@mjri...> wrote:
> I believe you can accomplish this by using the
> external signal 
> to "clock" timerA through the TACLK input. Then set
> the TACCR1 
> register to 1 and place it in compare mode. Also set
> the mode for 
> CCR1 so that the "OUT" bit goes high on
> EQUx(something like 
> TACTL1=OUT_3 and TACTL=MC_1+SSEL_0. Set CCR0 to some
> large number. 
> The ADC will  start conversion when the external
> signal goes high.
> 
> Mike 
> 
> --- In msp430@msp4..., onestone
> <onestone@b...> wrote:
> > Sumukh Pathare wrote:
> > > I am using MSP430F149. I would like to use the
> on-chip
> > > ADC to perform ADC on a signal when an external
> > > digital line goes from low to high. How can this
> be
> > > accomplished? The datasheet says that the
> on-chip ADC
> > > start-of-conversion can be controlled by:
> > > 1. ADC12SC (which is a on-chip bit settable in
> > > software)
> > > 2. Timer_A3.Out1
> > > 3. Timer_Bx.Out0 or
> > > 4. Timer_Bx.Out1.
> > > All these are internal signals.
> > 
> > I doubt that this will work, I've never tried it,
> but EQUx is set 
> on a 
> > capture event, and OUTx can be configured to SET
> on EQUx. I assume 
> that 
> > OUTx only does this in output mode, but it's worth
> seeing if OUTx 
> will 
> > follow EQUx in capture mode. Failing that you're
> basically stuck.
> > 
> > However, unless  under a microsecond of  jitter on
> the conversion 
> time 
> > is critical to your application the latency issue
> isn't a big deal. 
> The 
> > variation in interrupt latency is only between 1
> and 6 clock 
> cycles, 
> > being the shortest and longest instruction timings
> respectively. 
> The 
> > rest of the ISR latency is fixed. jitter is
> therefore just 625nsecs 
> at 
> > 8MHz. If this is an issue you'll need to go to an
> external 
> simultaneous 
> > dual conversion part.
> > 
> > Al
> > 
> > > 
> > > There doesn't seem to be a way by which an
> external
> > > event can trigger conversion, except making the
> > > external event to cause an interrupt and inside
> the
> > > ISR set the ADC12SC bit. I don't want to do that
> since
> > > it introduces variable latency in doing ADC.
> > > 
> > > Is there a way to make this happen?
> > > 
> > > -Sumukh
> > > 
> > > 
> > > __________________________________
> > > 
> > > 
> > > 
> > > .
> > > 
> > >  
> > > 
> > > ">http://docs.yahoo.com/info/terms/ 
> > > 
> > > 
> > >
> 
> 


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