Hi,

This ADC10 and its timing confuses me abit, the problem is as 
follows: 

i'm adding up the value from ADC10MEM in a variable (comparator), 
signaling when it reaches a threshold (Vtr), and i would expect the 
time it takes for Vtr to be reached to vary depending on frequency 
of the input signal, but it doesn't seem to do that. I wonder if 
anyone can explain to me a few things:

*what is the relationship between sample-and-hold time and sampling 
frequency? i dont really get why its possible to choose different 
sample-and-hold times...

*below is the settings im using, which doesn't seem to work 100% 
correctly..

ADC10CTL0 = SREF_1 + ADC10ON + REFOUT +
            REF2_5V + REFON + ADC10IE;

ADC10CTL1 = ADC10SSEL_1 + ADC10DIV_7;

Here, ACLK is chosen as source for ADC10CLK and ACLK's frequency 
divided by 8; So, f(ACLK) = 4096 Hz - correct? Does this mean that 
both sampling and conversion is run at this frequency? How can I 
make the ADC10 sample at approximately 1 kHz? Is it possible?

Thank you much!

Regards,

Kristine T.

hi kristine,


--- In msp430@msp4..., "lady_kbjt" <lady_kbjt@y...> wrote:
> Hi,
> 
> This ADC10 and its timing confuses me abit, the problem is as 
> follows: 
> 
> i'm adding up the value from ADC10MEM in a variable (comparator), 
> signaling when it reaches a threshold (Vtr), and i would expect the 
> time it takes for Vtr to be reached to vary depending on frequency 
> of the input signal,

if you mean the sampling frequency, not the frequency of some AC 
input signal you want to measure, then you're right.


 but it doesn't seem to do that. I wonder if 
> anyone can explain to me a few things:
> 
> *what is the relationship between sample-and-hold time and sampling 
> frequency? i dont really get why its possible to choose different 
> sample-and-hold times...

there is no relationship, they are 2 different things.
have a look at the user's guide e.g. slau49d.pdf, chapter "sample and 
conversion timing" (p. 18-7).
there is a timing diagram (fig. 18-3) which shows the ADC process.
what you call "sample-and-hold-time", is tsample in the diagram.
during this time, the input signal is sampled. one can imagine 
that "sampling" means charging an internal capacitor up to the analog 
input voltage by connecting the input pin to this capacitor.
after the sampling time is over, the connection is opened and the 
actual conversion starts. the conversion time is tconvert in fig. 18-
3.

page 18-8 in the user's guide explains how to calculate the required 
sampling time. it depends mainly on the source resistance of the 
analog signal.
first you calculate the required sampling time in microseconds, then, 
how many periods of ADC10CLK you need to get this sampling time.
round this up to the next possible value (you can only set 4,8,16,64 
x ADC10CLK cycles).


sampling freqency, which is the same as conversion frequency, is how 
many times per second you do the whole sample+conversion process.
this is totally independent of ADC10CLK. you can go as low as you 
want with sampling frequency, and as high as about 1/
(tsample+tconvert).

> 
> *below is the settings im using, which doesn't seem to work 100% 
> correctly..
> 
> ADC10CTL0 = SREF_1 + ADC10ON + REFOUT +
>             REF2_5V + REFON + ADC10IE;
> 
> ADC10CTL1 = ADC10SSEL_1 + ADC10DIV_7;
> 
> Here, ACLK is chosen as source for ADC10CLK and ACLK's frequency 
> divided by 8; So, f(ACLK) = 4096 Hz - correct? 

yes and no. the frequency is 4096 kHz, correct.
but you can't set the ADC10CLK this low. the minimum frequency 
according to the datasheet is 450kHz.
you'd better use ADC10OSC as clock source.


Does this mean that 
> both sampling and conversion is run at this
frequency? How can I 
> make the ADC10 sample at approximately 1 kHz? Is it possible?

it is possible. you can initiate AD conversion by software at any 
time and rate you want or use Timer_A to do this.


you don't seem to set the analog enable control bit in ADC10AE.


hope this helped

wolfgang

lady_kbjt wrote:

 > Does anyone know the highest frequency I can get out of, say timer A,
 > given an 8 Mhz mclock?  I'm hoping I can get a ~50% duty cycle
 > waveform at 4 Mhz, but I don't know if this is possible.
 > Setting values like 0 and 1 in the timers, in all the different modes,
 > might take me some time.  And the manual is not helpful in this limit
 > case.

You can output the crystal frequency on the I/O pins, or a divided by 
2,4 or 8 version of it, so the absolute answer is 8MHz in your case.

You an also use the compare unit in PWM mode, setting the period with 
CCR0 and the 50% duty cycle with CCR1, thus CCR0 = 2 and CCR1 = 1 would 
seem to give a maximum frequency half the clock source rate, however it 
would be simpler, in this case, to simply output the divided clock, the 
same for divisions of 4 and 8. I wouldn't try using PWM, or other direct 
(toggle) modes to output frequencies so close to the clock source, when 
a simpler method is available, and, in general the PWM method will be 
easier to handle than the toggle method, since no ISR is required to 
reload the CCRx register. You can of course use the 'count to' mode of

T3 on CCR0, but this limits the usefulness of the other timer channels 
when set to low values.

All of the above assume you just want to generate an external clock. 
However if you mean 'What frequency can I controllably output and 
interactively process data based upon the timer' (ie use an ISR to 
perfom timed functions) the answer depends solely upon how much more 
processign the application needs to do, ie how much of the processing 
capacity can you spare. The simplest, and most controllable way to 
create an output is using an ISR. This will give you some problems with 
jitter. I allow 17 clock cycles for ISR latency. This includes the RETI, 
but no significant processing. It also allows for the worst case 
instruction being executed at the time the interrupt is detected. The 
longest instruction executes in 6 cycles.  Thus your waveform 
potentially jitters by 0 to 5 clock cycles, if you carefully crafted 
your code to only use registers with no complex addressing modes you can 
reduce the bare ISR latency to 12 clocks. Now add a 4 clock instruction 
to XOr the port bit with a constant generator and you get 16 clock 
cycles per half wave, when manually toggled. Allowing for a minimal of 
external processing, the practical upper limit is clock frequency/40, so 
about 200kHz in your case.

Al