bogus comport on the 18F442

Started by Eirik Karlsen November 2, 2003
Q: does the UART really have to transmit ASCII(0) as the first
byte after processor reset?
I want the processor to transmit a start-up (boot) message
on the UART but I don't want ASCII(0) to be the first character.

The datasheet states that the TSR register is set to 00 after reset,
and as far as I can tell this data HAVE TO be shifted out before
new data can be loaded from the TXREG register.

Is this correct or have I overlooked something?



Actually I believe TSR is undefined at reset. TRMT is set, indicating
that TSR is empty. If TSR is empty, any load to TXREG will immediately
fall through to TSR.

Chad

--- Eirik Karlsen <> wrote:
> Q: does the UART really have to transmit ASCII(0) as the first
> byte after processor reset?
> I want the processor to transmit a start-up (boot) message
> on the UART but I don't want ASCII(0) to be the first character.
>
> The datasheet states that the TSR register is set to 00 after reset,
> and as far as I can tell this data HAVE TO be shifted out before
> new data can be loaded from the TXREG register.
>
> Is this correct or have I overlooked something? >


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