Hi, this is my first post in this forum. 

For personal research, I want to compare the performance of two microprocessor:
Intel 8051 and Sparc Leon3. In order to evaluate these, an execution of a set of  some representative functions is done through an ISS (Instruction Set  Simulator). Then, I collect statistics and trivially reason about data figured out from the simulation.

Since the core of the 8051 microcontroller that I'm using as reference does not have external memory neither a cache, I want to disabilitate the instruction cache and the data cache on the Leon3 to obtain comparable data with those of the first one.

I'm using TSIM for the simulation of Leon 3. I read on the data sheet that this use a control register to set the behaviour of the cache. So, I added an inline assembly instruction, to functions used in benchmark, that writes in this register and set the cache to disable. I'm sure that the bits in the register are changed but when I do the simulation I see the caches written. I can see this because of commands that I can tell to simulator. 

I'm here to ask if you can help with this problem or you have some ideas because I'm stuck.

First a disclaimer, I am not familiar with Leon 3 so this comment may be off mark.

You wrote: "I'm sure that the bits in the register are changed but when I do the simulation I see the caches written."

The fact that the cache is being written doesn't necessarily mean that it is enabled and contributing to read performance. Do you see a difference in performance in Leon 3 with vs. without the instructions that disable the cache?

The cache performance benefit occurs when you read data from the cache instead of from memory, saving some number of clock ticks in the read access.

The cache write should be transparent and not affect your performance one way or the other. As long as reads always go out to memory and never hit the cache, the cache is disabled even if it is updated on writes.