I am trying to read and write data on ADV7403 decoder IC on my designed board. I have been through almost all questions regarding I2C bus with ADV7403 but my problem still remains there. Actually the even addresses of all the chip can be read and write and are accessible, but whenever I try to write or read data from odd registers, the bus stuck. In writing it stuck on data acknowledge and doesn't give it. It gives the address acknowledge and sub address acknowledge. My code is working fine as I have tested it on many other devices. Power rails are checked with reset settings. Problem is only the odd addresses aren't responding and I have checked and verified on Oscillioscope as well. Both even and off cycles looks same.
Pull up values are 4.7kohm. Kindly help me as I am stuck in it.
1) SDA1 and SDA2 and SCK1 and SCK2 are tied together.
2) SDA and SCK are connected accordingly
3) Reset is in high state
4) I can write data on even registers and all acknowledgements are received back accordingly. Whenever I try to write on odd addresses or read them, the master doesn't receive the data acknowledge, though it receives the deice address and device sub address
5) Code in FPGA is working fine as I have implemented the same code on one of the EVAL-Kit of ADV7403 and it does all the operations. The schematic looks fine as i have used the referenced schematic to follow.
6) It makes sense to me if the device doesn't reply me from the start, but how is it even possible that half of the addresses works completely fine and the other half stuck in between.
7) I have tried different speed for the bus but still the response is same.
Carefully reread the device protocol. IIRC, the addresses have to be masked in, bit set or just a set of constants. The problem looks like something is clearing bit1, bit0 is R/W*. It's easy to cross that up.
I've written my own I2C handler, then Freescale (NXP) added the I2C module. Both worked fine, but to "roll your own" isn't trivial. Good Hunting... <<<)))
I am using a FPGA and have written my own driver for it. The same is working on the EVAL-kit of ADV7403 but not on my design. I dont think it even as a hardware issue as half of the IC operates perfectly fine. As I disable the ADCs using even registers, I can see load current reducing from the power supply, so that makes sense that IC is responding accordingly. I have seen so many responses but it seems like you can help me in there. Like can you please eloborate a bit more what you have said. Thanks
Do you need to do the double setup of the read data as detailed here:
https://ez.analog.com/video/f/q-a/10794/adv7181c-i...
I think it is referring to repeated start that is the part of the I2C standard. Yes, I have also applied the repeated start condition. I am unable to write/read the odd addresses. The same operations are working for even addresses.
Can you show that part of the schematic? I'm confused because the datasheet suggested connections and your description are confusing.
The connections are perfectly fine and OK and i have re re verified them. Half of the registers of ADV7403 I2C are working accordingly. If the connection would had been the case, I had not even able to read/write on even registers
Howdy, that's an assumption that may not be valid. Take a careful look at commands that work, I've had goofy coincidences like "everything that works had bit3 high".
Your best symptom is bit1 (=address bit0) is low on stuff that works. Write some kind of test routine that lets you toggle each bit. Something as simple as 2 bytes that you can alternate as output. Have byte2=$00 and byte1={$01, $02, $04, $08, $10, $20, $40, $80}. Send these into one of the I2C registers that works, but a spot that will allow read/write of any 8 bit value, don't be concerned what those values do to the chip. Write, read and verify that the I2C chip is getting all bits.
An alternative is to do this to a simple I2C->parallel output expander, like a PCA9554 or 9555. Then an o'scope makes it easy.
I'll stop here and await results. Good Hunting... <<<)))
Sure thanks sir,
What i will try is to first try to write all the possible combinations(00-FF) on a register which are working already, will see if it stuck somewhere otherwise read the latest value in it. If that goes good, then i will try for those odd addresses which aren't working.
About your alternatives, I am in no position to add any hardware. But thanks for the suggestion.
Anyways I am gonna try it straight away will update you about the results.
Saeed
Howdy, full $00 - $ff is best, but just a single bit in each position will show a stuck line faster. G.H. <<<)))
Dear Sir,
I have done this test, and it still works the same way. Any bit combination on even addresses work. And on odd it doesn't work in any case. Secondly the the problem is I am getting the sub address acknowledgement of odd addresses and after that something happen in slave device that it doesn't respond. Because only when the last bit of sub address is changed, it stops replying the data acknowledgement, data bits have nothing to do with it
Hmmm, this sounds like it's changing direction. The LSb is read/write* initially, so if it's changing the master and slave may both be waiting for the other. Anyway, it doesn't seem to be in hardware. So I'll suggest a careful comparison of the working vs non-working in executing protocol.
Actually the same code works for Eval-Kit of this decoder IC that is why I am confident at the software side like at eval kit both even and odd addresses are read/write accordingly with same code. But again i will see both codes and try to copy paste again. But irony is I copied the code for Eval-kit and it just worked after changing just the UCF and it didn't work in original.
