Summary

Miro Samek explains the confusing conventions behind ARM Cortex-M interrupt priorities and shows how to reason about NVIC priority fields in real systems. The article clarifies numbering, priority grouping, and practical implications for CMSIS and RTOS-based firmware so readers can correctly configure and debug interrupt behavior.

Key Takeaways

• Decode how Cortex-M stores priority bits and why apparent priority numbers can be misleading.
• Convert between raw IPR register values, CMSIS APIs, and human-friendly priority conventions.
• Configure NVIC priority grouping (PRIGROUP) to control preemption vs subpriority behavior.
• Use BASEPRI, PRIMASK and RTOS priority settings correctly to protect critical sections without breaking preemption.
• Avoid common pitfalls like misinterpreting shifted priority fields and mismatching RTOS interrupt ceilings.

Who Should Read This

Embedded firmware engineers working with ARM Cortex-M processors who need to configure or debug interrupt priorities in bare-metal or RTOS-based systems.

Still RelevantIntermediate

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