Neil Robertson worked at Scientific Atlanta, Cisco, and ST Micro doing RF design, System Design, and DSP design for cable TV set-top boxes and cable modems. He is retired and lives in Columbus, Ohio.

Digital PLL's -- Part 2

Neil Robertson June 15, 20165 comments

In Part 1, we found the time response of a 2nd order PLL with a proportional + integral (lead-lag) loop filter.  Now let’s look at this PLL in the Z-domain [1, 2].  We will find that the response is characterized by a loop natural frequency ωn and damping coefficient ζ. 

Having a Z-domain model of the DPLL will allow us to do three things:

Compute the values of loop filter proportional gain KL and integrator gain KI that give the desired loop natural...

Digital PLL's -- Part 1

Neil Robertson June 7, 201622 comments
1. Introduction

Figure 1.1 is a block diagram of a digital PLL (DPLL).  The purpose of the DPLL is to lock the phase of a numerically controlled oscillator (NCO) to a reference signal.  The loop includes a phase detector to compute phase error and a loop filter to set loop dynamic performance.  The output of the loop filter controls the frequency and phase of the NCO, driving the phase error to zero.

One application of the DPLL is to recover the timing in a digital...

Re: Live blog

Reply posted 3 years ago (03/29/2019)
I subbed teaching a class for a professor a long time ago.  It's surprisingly difficult to lecture to un-engaged students taking a required course outside their...

Live blog

New thread started 3 years ago
Good Job Stephane!Neil

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