I am using a DEMO9S12XDT512 Eval Board. This board is equipped with a
4.000MHz. crystal. I'm trying
to reconfigure the processor to use the internal PLL and bump up the
frequency. After configuring the appropriate
registers, and loading the program, the processor still runs at the
4.000MHz rate. However, if I single step
the writing of the SYNR register, then it runs at my desired frequency.
I try checking and waiting on the LOCK status
bit, but this does not help.
What is the procedure for changing the PLL frequency?
HCS12X PLL
Started by ●April 7, 2006
Reply by ●April 8, 20062006-04-08
--- In 6..., Michael Burgess wrote:
>
> What is the procedure for changing the PLL frequency?
>
Below code works for me on a S12X, I am using 16MHz crystal though.
OscFreq equ 16000 ;Enter Osc speed
initSYNR equ $01 ; mult by synr + 1 = 2 (24MHz)
initREFDV equ $00 ;
PLLSEL equ %10000000 ;PLL select bit
LOCK equ %00001000 ;lock status bit
PLLON equ %01000000 ;phase lock loop on bit
; Initialize clock generator and PLL
bclr CLKSEL,PLLSEL ;disengage PLL to system
bset PLLCTL,PLLON ;turn on PLL
movb #initSYNR,SYNR ;set PLL multiplier
movb #initREFDV,REFDV ;set PLL divider
nop
nop
nop
nop
brclr CRGFLG,LOCK,*+0 ;while (!(crg.crgflg.bit.lock==1))
bset CLKSEL,PLLSEL ;engage PLL to system
>
> What is the procedure for changing the PLL frequency?
>
Below code works for me on a S12X, I am using 16MHz crystal though.
OscFreq equ 16000 ;Enter Osc speed
initSYNR equ $01 ; mult by synr + 1 = 2 (24MHz)
initREFDV equ $00 ;
PLLSEL equ %10000000 ;PLL select bit
LOCK equ %00001000 ;lock status bit
PLLON equ %01000000 ;phase lock loop on bit
; Initialize clock generator and PLL
bclr CLKSEL,PLLSEL ;disengage PLL to system
bset PLLCTL,PLLON ;turn on PLL
movb #initSYNR,SYNR ;set PLL multiplier
movb #initREFDV,REFDV ;set PLL divider
nop
nop
nop
nop
brclr CRGFLG,LOCK,*+0 ;while (!(crg.crgflg.bit.lock==1))
bset CLKSEL,PLLSEL ;engage PLL to system
Reply by ●April 10, 20062006-04-10