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This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).

  

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LCC and two-operand targets   [2 Articles]

0
Brian Davis - May 24 2013
I've recently been working on an LCC machine description for the YARD-1, but have run into some strange LCC problems when a targeting a two operand machine having register local... LCC and two-operand targets

A new bytecoded CPU design

0
"arm7.developer" - Feb 26 2013
Research and implementation notes for a novel bytecoded CPU design here: http://www.fpgarelated.com/showarticle/44.php The cpu uses 8 or 9-bit tokens that indirect through a ... A new bytecoded CPU design

fpgasm - a low-level design language for Xilinx FPGAs

0
"arm7.developer" - Sep 11 2012
Hello, I would like to present to you an alternative to Verilog and VHDL - FPGA Assembler. I've been fiddling with FPGAs for a while. I've been working on some open source... fpgasm - a low-level design language for Xilinx FPGAs

Intro: My44: is running code

-2
rtfinch36 - Aug 23 2011
My44: 44 bit processor using 11 bit bytes Specs: ------ 12kB instruction cache (2k words) 512 regs (32 available at any one time) classic 5 stage pipeline single cycle inst... Intro: My44: is running code

State of the YARD

+1
Brian Davis - Aug 18 2011
It's been a long while since my last update [1] on the YARD-1 I've put together a draft document, , describing the current state of the YARD-1 architecture and instr... State of the YARD

Using DDR RAM   [44 Articles]

+1
rtstofer - Aug 12 2011
I bought a Digilent Spartan 3E Starter Board and it comes with 32M x 16 of DDR RAM. They don't provide a controller core. So I started over at OpenCores and downloaded a DDR co... Using DDR RAM

step by step cpu design using altera fpga   [15 Articles]

+1
SNFEDOGAN - Feb 28 2011
Hi everyone i am quite new to fpga, cpu design and group as well ... I am sure its asked zillion of times in this group but I need urgent help is there any book, internet pag... step by step cpu design using altera fpga

FPGA to ARM7 shared memory concept via wishbone.   [6 Articles]

+2
djam...@gmail.com - Aug 24 2010
Hello Everyone. well i have designed a system that contains -- altera cyclone 3 FPGA, with 50M clock -- altera epcs16 Flash (configuration device for cyclone3) -- an LPC2468 ... FPGA to ARM7 shared memory concept via wishbone.

Problem with Altera Video Input Daughtercard (DC-VIDEO-TVP5146N) -

+3
mani...@gmail.com - May 24 2010
> > Hello, > > Does somebody work with DC-VIDEO-TVP5146N Altera kit > > (http://www.altera.com/products/devkits/altera/kit-daughtercard.html) ? > > I try to connect DC-V... Problem with Altera Video Input Daughtercard (DC-VIDEO-TVP5146N) -

Problem with Altera Video Input Daughtercard (DC-VIDEO-TVP5146N)

+1
gmdi...@gmail.com - May 13 2010
Hello, Does somebody work with DC-VIDEO-TVP5146N Altera kit (http://www.altera.com/products/devkits/altera/kit-daughtercard.html) ? I try to connect DC-VIDEO-TVP5146N to DK-NI... Problem with Altera Video Input Daughtercard (DC-VIDEO-TVP5146N)
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