blewis999 wrote:
>"Speaking of ap notes, did you follow the suggested PC board layout?
>It seems to be fairly critical, because Freescale provides suggested
>layouts for several versions of this chip in the Device User Guide,
>section 23. Gary Olmstead"
Yes, we followed the Appnote 2727 and checked the design guide but
must have missed something. I almost seems like the cct is oscillating
on a harmonic rather then the fundemental freq. But again we can't
tell because we can't measure the oscillator frequency directly.
The schematic had been corrected and I missed the correction, there
are supposed to be (2) 22pf cap's in the oscillator cct. But to make
sure I removed them and put two new 22pf caps incase they had been wrong.
>"I see absolutely no reason to break the ground plane below the
>oscillator, and I also wouldn't make the slots in the groundplane
>below the controller. ...Oliver"
We used a four layer board and removed all the gnd and VCC planes
beneath the oscillator and pll as per the appnote. I think the design
guide did not use a 4 layer board. Is this an error on our part?
Thank you for the cct for the probe; I will build this as soon as we
can find the time. Right now I would be concerned that we would not
get this to work the first time and would be caught for time.
> "you can look at the CRGFLAG register
> to see if the SCM bit is set"
I checked the CRGFLAG register and I think the part is not in self
clock mode. Location 0x37 is 0x5C
which I believe is:
RTIF PORF 0 LOCKIF LOCK TRACK SCMIF SCM
0 1 0 1 1 1 0 0
so the oscillator is locked in and tracking I think, but at the wrong
frequency. I have 5 boards, 3 with a working oscillator, and two that
have the wrong frequency. I can see no difference in the boards and
have tried changing all the oscillator components on the 2 non working
boards to verify the parts. But still no success.
Someone had suggested a much higher resistance across the xtal; I
tried 10M but this produced a higher freq and not the desired 16M.
What exactly that freq is I can't tell because I can't measure it.
>"I have no problem probing either pins on the pierce oscillator
>configured crystal with 10M ohm oscilloscope probe. If it does not
>oscillate it's not working or does not have enough margin.
>Andrew"
I did capture the oscillator waveform from another (different design)
board that has the oscillator working correctly and it looked like a
dc offset sine wave, although the zero crossing points where not
symmetrical neither was the waveform. Since I don't think I can post
the picture this is the best I can describe it. But the boards (all 5,
even the three that work) must have a very weak oscillator output
because can not see it at all on the scope.
>"Another recommendation is to make sure you actually measure 2.5V on
>both
>the VDD and the VDDPLL pins. Doron"
We have 2.5v and about 60mv of switching noise at periodic points.
If I post a capture of the oscillator section of the pcb board would
that be of any value? Or is there a way to do this even?
Thanks for the suggestions and help.
Bob Lewis
>
> I will try this in the morning.
>
> Thanks for the help
>
> Bob Lewis
>
werial port error & crystal freq measurement method for a 9s12dg128
Started by ●June 1, 2006
Reply by ●June 12, 20062006-06-12
Reply by ●June 13, 20062006-06-13
Bob,
At 16:22 12/06/2006 -0700, you wrote:
>I did capture the oscillator waveform from another (different design)
>board that has the oscillator working correctly and it looked like a
>dc offset sine wave, although the zero crossing points where not
>symmetrical neither was the waveform. Since I don't think I can post
>the picture this is the best I can describe it. But the boards (all 5,
>even the three that work) must have a very weak oscillator output
>because can not see it at all on the scope.
The fact you cannot measure the crystal frequency on your 5 new boards, but
can on another design hints back to the PE7/XCLKS signal.
If PE7/XCLKS has a low level during Reset, or has a non-valid logic 0, or
is not continued to be held low for a short duration after Reset (for
positive hold time), your 9S12DG128 CPU will be forced to the Colpitts
crystal configuration (which exhibits low amplitude on the EXTAL and XTAL
signals), rather than the full-swing Pierce oscillator that you are trying
to use.
Instead of you I would go back to the PE7/XCLKS signal and measure it in
parallel with the Reset signal using an Oscilloscope.
Hope this helps,
Doron
Nohau
HC12 In-Circuit Emulators
www.nohau.com/emul12pc.html
At 16:22 12/06/2006 -0700, you wrote:
>I did capture the oscillator waveform from another (different design)
>board that has the oscillator working correctly and it looked like a
>dc offset sine wave, although the zero crossing points where not
>symmetrical neither was the waveform. Since I don't think I can post
>the picture this is the best I can describe it. But the boards (all 5,
>even the three that work) must have a very weak oscillator output
>because can not see it at all on the scope.
The fact you cannot measure the crystal frequency on your 5 new boards, but
can on another design hints back to the PE7/XCLKS signal.
If PE7/XCLKS has a low level during Reset, or has a non-valid logic 0, or
is not continued to be held low for a short duration after Reset (for
positive hold time), your 9S12DG128 CPU will be forced to the Colpitts
crystal configuration (which exhibits low amplitude on the EXTAL and XTAL
signals), rather than the full-swing Pierce oscillator that you are trying
to use.
Instead of you I would go back to the PE7/XCLKS signal and measure it in
parallel with the Reset signal using an Oscilloscope.
Hope this helps,
Doron
Nohau
HC12 In-Circuit Emulators
www.nohau.com/emul12pc.html
Reply by ●June 13, 20062006-06-13
Doron Fael wrote:
>
> The fact you cannot measure the crystal frequency on your 5 new boards, but
> can on another design hints back to the PE7/XCLKS signal.
>
> If PE7/XCLKS has a low level during Reset
Doron, we have a low level during reset because the XCLKS signal is
tied to gnd permanently (I thought) to select the Pierce
configuration. Should the pin be high during reset to select the
oscilator cct, then brought low to select the Pierce oscillator cct?
Now that you mentioned this I re-read the section from the manual and
maybe that is what is being said. I had taken the 'external clock
drive' to mean the ability to use a canned oscillator, not to drive
the xtal pin or is this wrong?. If so can you suggest how is this
normally done please?
"The state of this pin is latched at the rising edge of RESET. If the
input is a logic low the EXTAL pin is configured for an
external clock drive. If input is a logic high an oscillator circuit
is configured on EXTAL and XTAL. Since this pin is an input with a
pull-up device during reset, if the pin is left floating, the default
configuration is
an oscillator circuit on EXTAL and XTAL."
, or has a non-valid logic 0, or
> is not continued to be held low for a short duration after Reset (for
> positive hold time), your 9S12DG128 CPU will be forced to the Colpitts
> crystal configuration (which exhibits low amplitude on the EXTAL and XTAL
> signals), rather than the full-swing Pierce oscillator that you are trying
> to use.
>
> Instead of you I would go back to the PE7/XCLKS signal and measure it in
> parallel with the Reset signal using an Oscilloscope.
Doron
This is exact
>
> The fact you cannot measure the crystal frequency on your 5 new boards, but
> can on another design hints back to the PE7/XCLKS signal.
>
> If PE7/XCLKS has a low level during Reset
Doron, we have a low level during reset because the XCLKS signal is
tied to gnd permanently (I thought) to select the Pierce
configuration. Should the pin be high during reset to select the
oscilator cct, then brought low to select the Pierce oscillator cct?
Now that you mentioned this I re-read the section from the manual and
maybe that is what is being said. I had taken the 'external clock
drive' to mean the ability to use a canned oscillator, not to drive
the xtal pin or is this wrong?. If so can you suggest how is this
normally done please?
"The state of this pin is latched at the rising edge of RESET. If the
input is a logic low the EXTAL pin is configured for an
external clock drive. If input is a logic high an oscillator circuit
is configured on EXTAL and XTAL. Since this pin is an input with a
pull-up device during reset, if the pin is left floating, the default
configuration is
an oscillator circuit on EXTAL and XTAL."
, or has a non-valid logic 0, or
> is not continued to be held low for a short duration after Reset (for
> positive hold time), your 9S12DG128 CPU will be forced to the Colpitts
> crystal configuration (which exhibits low amplitude on the EXTAL and XTAL
> signals), rather than the full-swing Pierce oscillator that you are trying
> to use.
>
> Instead of you I would go back to the PE7/XCLKS signal and measure it in
> parallel with the Reset signal using an Oscilloscope.
Doron
This is exact
Reply by ●June 14, 20062006-06-14
Hi Bob,
At 12:25 13/06/2006 -0700, you wrote:
>Doron, we have a low level during reset because the XCLKS signal is
>tied to gnd permanently (I thought) to select the Pierce
>configuration.
A permanent low level on the XCLKS pin of the 9S12DG128 should be fine to
select the Pierce Crystal configuration that you try to use.
A low level on XCLKS during Reset rise is used to select either an external
Clock Generator (external square wave clock source) or the Pierce Crystal
configuration.
A high level on XCLKS during Reset rise is used to select the Colpitts
Crystal configuration.
Going back to your problem:
My suggestion is to hook a logic analyzer and/or an oscilloscope to measure
the actual signals, rather than rely on the schematics - as they sometime
don't represent what's implemented in reality due to PCB layout mistakes.
The signals to measure are all the basic pins involved in the most
fundamental operation of the CPU. I have seen layout mistakes/problems in
too many customer designs around these points.
The signals I suggest to measure are:
VDDX, VDDR, VDDA and VRH should all be 5V (or 3.3V).
VSSX, VSSR, VSSA, VRL, VSSPLL, VSS, and TEST should all be 0V - GND.
RESET
The following signal must have positive hold time after Reset rise, to
force the desired operation mode and clock-generator mode:
BKGD/MODC
PE6/MODB
PE5/MODA
PE7/XCLKS
Pay attention especially to the Reset pin.
Improper Reset signal setup is often source of many problems with the
HCS12, if charged too slow from 0 to 1. It is highly recommended to use an
external Reset IC that holds Reset low for 100mSEC or more after valid
power is detected, and then tri-states and uses a relatively low-resistance
pull-up resistor (4.7Kohm should be good), to bring Reset from low to high
in a short period. High capacitors on the Reset line are known to cause
many problems. if you must use a Cap on Reset for noise immunity, don't use
a Cap larger than 100pF.
Hope this helps,
Doron
Nohau
HC12 In-Circuit Emulators
www.nohau.com/emul12pc.html
At 12:25 13/06/2006 -0700, you wrote:
>Doron, we have a low level during reset because the XCLKS signal is
>tied to gnd permanently (I thought) to select the Pierce
>configuration.
A permanent low level on the XCLKS pin of the 9S12DG128 should be fine to
select the Pierce Crystal configuration that you try to use.
A low level on XCLKS during Reset rise is used to select either an external
Clock Generator (external square wave clock source) or the Pierce Crystal
configuration.
A high level on XCLKS during Reset rise is used to select the Colpitts
Crystal configuration.
Going back to your problem:
My suggestion is to hook a logic analyzer and/or an oscilloscope to measure
the actual signals, rather than rely on the schematics - as they sometime
don't represent what's implemented in reality due to PCB layout mistakes.
The signals to measure are all the basic pins involved in the most
fundamental operation of the CPU. I have seen layout mistakes/problems in
too many customer designs around these points.
The signals I suggest to measure are:
VDDX, VDDR, VDDA and VRH should all be 5V (or 3.3V).
VSSX, VSSR, VSSA, VRL, VSSPLL, VSS, and TEST should all be 0V - GND.
RESET
The following signal must have positive hold time after Reset rise, to
force the desired operation mode and clock-generator mode:
BKGD/MODC
PE6/MODB
PE5/MODA
PE7/XCLKS
Pay attention especially to the Reset pin.
Improper Reset signal setup is often source of many problems with the
HCS12, if charged too slow from 0 to 1. It is highly recommended to use an
external Reset IC that holds Reset low for 100mSEC or more after valid
power is detected, and then tri-states and uses a relatively low-resistance
pull-up resistor (4.7Kohm should be good), to bring Reset from low to high
in a short period. High capacitors on the Reset line are known to cause
many problems. if you must use a Cap on Reset for noise immunity, don't use
a Cap larger than 100pF.
Hope this helps,
Doron
Nohau
HC12 In-Circuit Emulators
www.nohau.com/emul12pc.html
Reply by ●June 15, 20062006-06-15
Doron Fael and everyone
I thought I would post with the solution of the problem.
What I found was a cold solder joint on the crystal. I had used a
through hole part to solder onto the pads of an smd crystal. One of
the leads had a cold solder joint. I found it when I had to bend the
part slightly to access the micro's pins and it didn't feel right. A
bit more movement and it broke free. Once it was soldered I could see
the signal. Why the micro wasn't in self clock mode is a mystery, but
I guess the resistance added enough of a shift of freq to mess up the
serial connection. I wouldn't have found this without the serial
connecton because all the spi parts worked fine... The baud rate
couldn't be set with the crystal freq off.
Well a lesson learned... but what a time sink...
Thank you for your suggestions, they helped me in searching out and
trying to understand the problem.
Bob
I thought I would post with the solution of the problem.
What I found was a cold solder joint on the crystal. I had used a
through hole part to solder onto the pads of an smd crystal. One of
the leads had a cold solder joint. I found it when I had to bend the
part slightly to access the micro's pins and it didn't feel right. A
bit more movement and it broke free. Once it was soldered I could see
the signal. Why the micro wasn't in self clock mode is a mystery, but
I guess the resistance added enough of a shift of freq to mess up the
serial connection. I wouldn't have found this without the serial
connecton because all the spi parts worked fine... The baud rate
couldn't be set with the crystal freq off.
Well a lesson learned... but what a time sink...
Thank you for your suggestions, they helped me in searching out and
trying to understand the problem.
Bob
