Hello
I am new on this list. Reading the list archive tells me that I may be
in a right place with my questions. I am planing to start
experimenting with my Jeep Renegade PCI (J1850 VPWM) bus. I designed
small board for my software experiment platform. This is my first
MC9S12DJ64 design. Many of you have lots of experience with MC9S12
designs. Please let me know if you have any comments about my board.
Early documentation of my project can be found here:
http://www.kolumbus.fi/juha.niinikoski/J1850/J1850converter.htm
I have also searched web for BDLC sample code and application notes
but found nothing. Please let me kdow if such material excists
somewhere. I have SAE HS-3000 standard set (1998 edition) for
background reading.
Juha
J1850 converter / display
Started by ●May 11, 2007
Reply by ●May 11, 20072007-05-11
1) You need to have something like MC34064 on /RESET pin.
2) VREGEN should be tied to VCC.
3) VDD2, VDD1 must be NOT connected to 5V VCC! VDD1 and VDD2 are the outputs
of internal ~2.5V regulator. IIRC 0.22uF bypass caps must be between
VSS1-VDD1 and VSS2-VDD2.
Edward
----- Original Message -----
From: "Juha"
To: <6...>
Sent: Friday, May 11, 2007 22:06
Subject: [68HC12] J1850 converter / display
> Hello
> I am new on this list. Reading the list archive tells me that I may be
> in a right place with my questions. I am planing to start
> experimenting with my Jeep Renegade PCI (J1850 VPWM) bus. I designed
> small board for my software experiment platform. This is my first
> MC9S12DJ64 design. Many of you have lots of experience with MC9S12
> designs. Please let me know if you have any comments about my board.
> Early documentation of my project can be found here:
>
> http://www.kolumbus.fi/juha.niinikoski/J1850/J1850converter.htm
>
> I have also searched web for BDLC sample code and application notes
> but found nothing. Please let me kdow if such material excists
> somewhere. I have SAE HS-3000 standard set (1998 edition) for
> background reading.
>
> Juha
2) VREGEN should be tied to VCC.
3) VDD2, VDD1 must be NOT connected to 5V VCC! VDD1 and VDD2 are the outputs
of internal ~2.5V regulator. IIRC 0.22uF bypass caps must be between
VSS1-VDD1 and VSS2-VDD2.
Edward
----- Original Message -----
From: "Juha"
To: <6...>
Sent: Friday, May 11, 2007 22:06
Subject: [68HC12] J1850 converter / display
> Hello
> I am new on this list. Reading the list archive tells me that I may be
> in a right place with my questions. I am planing to start
> experimenting with my Jeep Renegade PCI (J1850 VPWM) bus. I designed
> small board for my software experiment platform. This is my first
> MC9S12DJ64 design. Many of you have lots of experience with MC9S12
> designs. Please let me know if you have any comments about my board.
> Early documentation of my project can be found here:
>
> http://www.kolumbus.fi/juha.niinikoski/J1850/J1850converter.htm
>
> I have also searched web for BDLC sample code and application notes
> but found nothing. Please let me kdow if such material excists
> somewhere. I have SAE HS-3000 standard set (1998 edition) for
> background reading.
>
> Juha
Reply by ●May 11, 20072007-05-11
Edward,
thank you for your valuable comments. This kind of stupid errors
usually happens when you are working with completelly new
architecture. Found issues are now corrected and updated schematics is
at the same place as original.
Juha
--- In 6..., "Edward Karpicz" wrote:
>
> 1) You need to have something like MC34064 on /RESET pin.
>
> 2) VREGEN should be tied to VCC.
>
> 3) VDD2, VDD1 must be NOT connected to 5V VCC! VDD1 and VDD2 are the
outputs
> of internal ~2.5V regulator. IIRC 0.22uF bypass caps must be between
> VSS1-VDD1 and VSS2-VDD2.
>
> Edward
> ----- Original Message -----
> From: "Juha"
> To: <6...>
> Sent: Friday, May 11, 2007 22:06
> Subject: [68HC12] J1850 converter / display
> > Hello
> > I am new on this list. Reading the list archive tells me that I may be
> > in a right place with my questions. I am planing to start
> > experimenting with my Jeep Renegade PCI (J1850 VPWM) bus. I designed
> > small board for my software experiment platform. This is my first
> > MC9S12DJ64 design. Many of you have lots of experience with MC9S12
> > designs. Please let me know if you have any comments about my board.
> > Early documentation of my project can be found here:
> >
> > http://www.kolumbus.fi/juha.niinikoski/J1850/J1850converter.htm
> >
> > I have also searched web for BDLC sample code and application notes
> > but found nothing. Please let me kdow if such material excists
> > somewhere. I have SAE HS-3000 standard set (1998 edition) for
> > background reading.
> >
> > Juha
>
thank you for your valuable comments. This kind of stupid errors
usually happens when you are working with completelly new
architecture. Found issues are now corrected and updated schematics is
at the same place as original.
Juha
--- In 6..., "Edward Karpicz" wrote:
>
> 1) You need to have something like MC34064 on /RESET pin.
>
> 2) VREGEN should be tied to VCC.
>
> 3) VDD2, VDD1 must be NOT connected to 5V VCC! VDD1 and VDD2 are the
outputs
> of internal ~2.5V regulator. IIRC 0.22uF bypass caps must be between
> VSS1-VDD1 and VSS2-VDD2.
>
> Edward
> ----- Original Message -----
> From: "Juha"
> To: <6...>
> Sent: Friday, May 11, 2007 22:06
> Subject: [68HC12] J1850 converter / display
> > Hello
> > I am new on this list. Reading the list archive tells me that I may be
> > in a right place with my questions. I am planing to start
> > experimenting with my Jeep Renegade PCI (J1850 VPWM) bus. I designed
> > small board for my software experiment platform. This is my first
> > MC9S12DJ64 design. Many of you have lots of experience with MC9S12
> > designs. Please let me know if you have any comments about my board.
> > Early documentation of my project can be found here:
> >
> > http://www.kolumbus.fi/juha.niinikoski/J1850/J1850converter.htm
> >
> > I have also searched web for BDLC sample code and application notes
> > but found nothing. Please let me kdow if such material excists
> > somewhere. I have SAE HS-3000 standard set (1998 edition) for
> > background reading.
> >
> > Juha
>
Reply by ●May 12, 20072007-05-12
Juha,
I've no experience with J1850 but circuit now looks promising. Regards and
good luck.
Edward
----- Original Message -----
From: "Juha"
To: <6...>
Sent: Saturday, May 12, 2007 01:57
Subject: [68HC12] Re: J1850 converter / display
> Edward,
> thank you for your valuable comments. This kind of stupid errors
> usually happens when you are working with completelly new
> architecture. Found issues are now corrected and updated schematics is
> at the same place as original.
>
> Juha
>
> --- In 6..., "Edward Karpicz" wrote:
>>
>> 1) You need to have something like MC34064 on /RESET pin.
>>
>> 2) VREGEN should be tied to VCC.
>>
>> 3) VDD2, VDD1 must be NOT connected to 5V VCC! VDD1 and VDD2 are the
> outputs
>> of internal ~2.5V regulator. IIRC 0.22uF bypass caps must be between
>> VSS1-VDD1 and VSS2-VDD2.
>>
>> Edward
>> ----- Original Message -----
>> From: "Juha"
>> To: <6...>
>> Sent: Friday, May 11, 2007 22:06
>> Subject: [68HC12] J1850 converter / display
>> > Hello
>> > I am new on this list. Reading the list archive tells me that I may be
>> > in a right place with my questions. I am planing to start
>> > experimenting with my Jeep Renegade PCI (J1850 VPWM) bus. I designed
>> > small board for my software experiment platform. This is my first
>> > MC9S12DJ64 design. Many of you have lots of experience with MC9S12
>> > designs. Please let me know if you have any comments about my board.
>> > Early documentation of my project can be found here:
>> >
>> > http://www.kolumbus.fi/juha.niinikoski/J1850/J1850converter.htm
>> >
>> > I have also searched web for BDLC sample code and application notes
>> > but found nothing. Please let me kdow if such material excists
>> > somewhere. I have SAE HS-3000 standard set (1998 edition) for
>> > background reading.
>> >
>> > Juha
>>
> Yahoo! Groups Links
I've no experience with J1850 but circuit now looks promising. Regards and
good luck.
Edward
----- Original Message -----
From: "Juha"
To: <6...>
Sent: Saturday, May 12, 2007 01:57
Subject: [68HC12] Re: J1850 converter / display
> Edward,
> thank you for your valuable comments. This kind of stupid errors
> usually happens when you are working with completelly new
> architecture. Found issues are now corrected and updated schematics is
> at the same place as original.
>
> Juha
>
> --- In 6..., "Edward Karpicz" wrote:
>>
>> 1) You need to have something like MC34064 on /RESET pin.
>>
>> 2) VREGEN should be tied to VCC.
>>
>> 3) VDD2, VDD1 must be NOT connected to 5V VCC! VDD1 and VDD2 are the
> outputs
>> of internal ~2.5V regulator. IIRC 0.22uF bypass caps must be between
>> VSS1-VDD1 and VSS2-VDD2.
>>
>> Edward
>> ----- Original Message -----
>> From: "Juha"
>> To: <6...>
>> Sent: Friday, May 11, 2007 22:06
>> Subject: [68HC12] J1850 converter / display
>> > Hello
>> > I am new on this list. Reading the list archive tells me that I may be
>> > in a right place with my questions. I am planing to start
>> > experimenting with my Jeep Renegade PCI (J1850 VPWM) bus. I designed
>> > small board for my software experiment platform. This is my first
>> > MC9S12DJ64 design. Many of you have lots of experience with MC9S12
>> > designs. Please let me know if you have any comments about my board.
>> > Early documentation of my project can be found here:
>> >
>> > http://www.kolumbus.fi/juha.niinikoski/J1850/J1850converter.htm
>> >
>> > I have also searched web for BDLC sample code and application notes
>> > but found nothing. Please let me kdow if such material excists
>> > somewhere. I have SAE HS-3000 standard set (1998 edition) for
>> > background reading.
>> >
>> > Juha
>>
> Yahoo! Groups Links
Reply by ●May 12, 20072007-05-12
If the ip for the bdlc in this chip is the same as for the dp256 then
I'd say the J1850 is crappy. Too bad Moto phased out the mc68hc58
because the internal bdlc state machine doesn't play well with other
interrupts.
-rob
Edward Karpicz wrote:
> Juha,
>
> I've no experience with J1850 but circuit now looks promising. Regards and
> good luck.
>
> Edward
>
> ----- Original Message -----
> From: "Juha" > >
> To: <68HC12@yahoogroups. com
<
I'd say the J1850 is crappy. Too bad Moto phased out the mc68hc58
because the internal bdlc state machine doesn't play well with other
interrupts.
-rob
Edward Karpicz wrote:
> Juha,
>
> I've no experience with J1850 but circuit now looks promising. Regards and
> good luck.
>
> Edward
>
> ----- Original Message -----
> From: "Juha" > >
> To: <68HC12@yahoogroups. com
<
Reply by ●May 26, 20072007-05-26
Two weeks ago I draw simple test board schematics. Thank's for some
list members for valuable comments about the schematics. MC9S12xx
devices and CodeWarrior environment are new things for me. Couple of
days ago I got my PCBs and populated them. Today I had a break through
with board tests. My thing reads meaningful data from Jeep bus. For
those who are interested brief documentation can be found here.
http://www.kolumbus.fi/juha.niinikoski/J1850/J1850converter.htm
I appreciate further comments and notices. Somebody mentioned about
"crappy" BDLC interface in MC12S parts. Somehow I have not had any
difficulties with this I/O device. It is complicated but everything
works as specified(or I have not yet found the catch). I am interested
to hear details about the problems. Next step is to clean up my test
software and implement more OBD-II protocol functions. Most
interesting part will be finding out secrets of Chrysler private
module to module protocols. There is lots of traffic on the bus.
list members for valuable comments about the schematics. MC9S12xx
devices and CodeWarrior environment are new things for me. Couple of
days ago I got my PCBs and populated them. Today I had a break through
with board tests. My thing reads meaningful data from Jeep bus. For
those who are interested brief documentation can be found here.
http://www.kolumbus.fi/juha.niinikoski/J1850/J1850converter.htm
I appreciate further comments and notices. Somebody mentioned about
"crappy" BDLC interface in MC12S parts. Somehow I have not had any
difficulties with this I/O device. It is complicated but everything
works as specified(or I have not yet found the catch). I am interested
to hear details about the problems. Next step is to clean up my test
software and implement more OBD-II protocol functions. Most
interesting part will be finding out secrets of Chrysler private
module to module protocols. There is lots of traffic on the bus.
Reply by ●May 27, 20072007-05-27
If your device is dedicated to J1850 then the bdlc is fine. I'm glad
you've had success. The problem is that an interrupt driven
architecture that has many possible sources of interrupt can disrupt the
bdlc fsm and cause lose of information. The asynchronous implementation
requires synchronous interrupt handling. Nutty.
A Motorola eng told me that I'd have to disable the SCI rx interrupt to
ensure clean bdlc rx. I settled on putting it at the top of HPRIO.
This is why I prefer the HC58 solution.
-rob
Juha wrote:
> Two weeks ago I draw simple test board schematics. Thank's for some
> list members for valuable comments about the schematics. MC9S12xx
> devices and CodeWarrior environment are new things for me. Couple of
> days ago I got my PCBs and populated them. Today I had a break through
> with board tests. My thing reads meaningful data from Jeep bus. For
> those who are interested brief documentation can be found here.
>
> http://www.kolumbus .fi/juha. niinikoski/ J1850/J1850conve rter.htm
> I appreciate further comments and notices. Somebody mentioned about
> "crappy" BDLC interface in MC12S parts. Somehow I have not had any
> difficulties with this I/O device. It is complicated but everything
> works as specified(or I have not yet found the catch). I am interested
> to hear details about the problems. Next step is to clean up my test
> software and implement more OBD-II protocol functions. Most
> interesting part will be finding out secrets of Chrysler private
> module to module protocols. There is lots of traffic on the bus.
you've had success. The problem is that an interrupt driven
architecture that has many possible sources of interrupt can disrupt the
bdlc fsm and cause lose of information. The asynchronous implementation
requires synchronous interrupt handling. Nutty.
A Motorola eng told me that I'd have to disable the SCI rx interrupt to
ensure clean bdlc rx. I settled on putting it at the top of HPRIO.
This is why I prefer the HC58 solution.
-rob
Juha wrote:
> Two weeks ago I draw simple test board schematics. Thank's for some
> list members for valuable comments about the schematics. MC9S12xx
> devices and CodeWarrior environment are new things for me. Couple of
> days ago I got my PCBs and populated them. Today I had a break through
> with board tests. My thing reads meaningful data from Jeep bus. For
> those who are interested brief documentation can be found here.
>
> http://www.kolumbus .fi/juha. niinikoski/ J1850/J1850conve rter.htm
> I appreciate further comments and notices. Somebody mentioned about
> "crappy" BDLC interface in MC12S parts. Somehow I have not had any
> difficulties with this I/O device. It is complicated but everything
> works as specified(or I have not yet found the catch). I am interested
> to hear details about the problems. Next step is to clean up my test
> software and implement more OBD-II protocol functions. Most
> interesting part will be finding out secrets of Chrysler private
> module to module protocols. There is lots of traffic on the bus.
