My program is 1.4MB and I am loading into SDRAM. I use the
init_sdram.gdb file to initialize the SDRAM before loading the
program. In Jlink-gdb server I checked the verify download box to
verify. It fails after going back to normal mode in init_sdram but
the program is loaded succesfully. Can anyone please let me know what
needs to be modified in my init_sdram.gdb file to verify pass? Below
is the init_sdram.gdb contents
-
# Change to default reset behavior
monitor long 0xFFFFFD08 0x401
# Reset peripherals
monitor long 0xFFFFFd00 0x4
# Unremap
monitor long 0xFFFFEF00 0x0
# Zero out registers
monitor reset 6
# Disable and clear AIC interrupt sources (important!)
monitor long 0xFFFFF124 0xFFFFFFFF
monitor long 0xFFFFF128 0xFFFFFFFF
monitor reset
monitor speed 30
monitor speed adaptive
# Disable watchdog
monitor long 0xfffffd44 0x30008000
# Configure master clock
echo Configuring the master clock...\n
# Enable main oscillator
set *0xFFFFFC20 = 0x00004001
while ((*0xFFFFFC68 & 0x1) == 0)
end
# Switch to main oscillator
set *0xFFFFFC30 = 0x00000001
# Set PLLA to 200MHz
set *0xFFFFFC28 = 0x2095BF0F
while ((*0xFFFFFC68 & 0x2) == 0)
end
while ((*0xFFFFFC68 & 0x1) == 0)
end
# Select prescaler
set *0xFFFFFC30 = 0x00000101
while ((*0xFFFFFC68 & 0x8) == 0)
end
# Select master clock based on PLLA
set *0xFFFFFC30 = 0x00000102
while ((*0xFFFFFC68 & 0x8) == 0)
end
echo Master clock ok.\n
echo Configuring the SDRAM controller...\n
# Enable EBI chip select for the SDRAM
set *0xFFFFEF20 = 0x2
# SDRAM configuration
set *0xFFFFEA08 = 0x852272D0
set *0xFFFFEA00 = 0x1
set *0x20000000 = 0
set *0xFFFFEA00 = 0x2
set *0x20000000 = 0
set *0xFFFFEA00 = 0x4
set *0x20000000 = 0
set *0xFFFFEA00 = 0x4
set *0x20000000 = 0
set *0xFFFFEA00 = 0x4
set *0x20000000 = 0
set *0xFFFFEA00 = 0x4
set *0x20000000 = 0
set *0xFFFFEA00 = 0x4
set *0x20000000 = 0
set *0xFFFFEA00 = 0x4
set *0x20000000 = 0
set *0xFFFFEA00 = 0x4
set *0x20000000 = 0
set *0xFFFFEA00 = 0x4
set *0x20000000 = 0
set *0xFFFFEA00 = 0x3
set *0x20000000 = 0
set *0xFFFFEA00 = 0x0
set *0x20000000 = 0
set *0xFFFFEA04 = 0x2B7
echo SDRAM configuration ok.\n
--------------------
Jlink-gdb partial output:
*****************************
Connected to 127.0.0.1
SAM-ICE found !
Reading all registers
Read 4 bytes @ address 0x00000000 (Data = 0xEA000006)
Read 4 bytes @ address 0x00000000 (Data = 0xEA000006)
Resetting target (halt with breakpoint @ address 0)
Writing 0x00000401 @ address 0xFFFFFD08
Writing 0x00000004 @ address 0xFFFFFD00
Writing 0x00000000 @ address 0xFFFFEF00
Resetting target (soft reset)
Writing 0xFFFFFFFF @ address 0xFFFFF124
Writing 0xFFFFFFFF @ address 0xFFFFF128
Resetting target
JTAG speed set to 30 kHz
Select adaptive clocking instead of fixed JTAG speed
Writing 0x30008000 @ address 0xFFFFFD44
Downloading 4 bytes @ address 0xFFFFFC20 - Verified OK
Read 4 bytes @ address 0x00000000 (Data = 0xEA000006)
Read 4 bytes @ address 0xFFFFFC68 (Data = 0x00000009)
Downloading 4 bytes @ address 0xFFFFFC30 - Verified OK
Read 4 bytes @ address 0x00000000 (Data = 0xEA000006)
Downloading 4 bytes @ address 0xFFFFFC28 - Verified OK
Read 4 bytes @ address 0x00000000 (Data = 0xEA000006)
Read 4 bytes @ address 0xFFFFFC68 (Data = 0x0000000B)
Read 4 bytes @ address 0xFFFFFC68 (Data = 0x0000000B)
Downloading 4 bytes @ address 0xFFFFFC30 - Verified OK
Read 4 bytes @ address 0x00000000 (Data = 0xEA000006)
Read 4 bytes @ address 0xFFFFFC68 (Data = 0x0000000B)
Downloading 4 bytes @ address 0xFFFFFC30 - Verified OK
Read 4 bytes @ address 0x00000000 (Data = 0xEA000006)
Read 4 bytes @ address 0xFFFFFC68 (Data = 0x0000000B)
Downloading 4 bytes @ address 0xFFFFEF20 - Verified OK
Read 4 bytes @ address 0x00000000 (Data = 0xEA000006)
Downloading 4 bytes @ address 0xFFFFEA08 - Verified OK
Read 4 bytes @ address 0x00000000 (Data = 0xEA000006)
Downloading 4 bytes @ address 0xFFFFEA00 - Verified OK
Read 4 bytes @ address 0x00000000 (Data = 0xEA000006)
Downloading 4 bytes @ address 0x20000000 - Verified OK
Read 4 bytes @ address 0x00000000 (Data = 0xEA000006)
Downloading 4 bytes @ address 0xFFFFEA00 - Verified OK
Read 4 bytes @ address 0x00000000 (Data = 0xEA000006)
Downloading 4 bytes @ address 0x20000000 - Verified OK
Read 4 bytes @ address 0x00000000 (Data = 0xEA000006)
Downloading 4 bytes @ address 0xFFFFEA00 - Verified OK
Read 4 bytes @ address 0x00000000 (Data = 0xEA000006)
Downloading 4 bytes @ address 0x20000000 - Verified OK
Read 4 bytes @ address 0x00000000 (Data = 0xEA000006)
Downloading 4 bytes @ address 0xFFFFEA00 - Verified OK
Read 4 bytes @ address 0x00000000 (Data = 0xEA000006)
Downloading 4 bytes @ address 0x20000000 - Verified OK
Read 4 bytes @ address 0x00000000 (Data = 0xEA000006)
Downloading 4 bytes @ address 0xFFFFEA00 - Verified OK
Read 4 bytes @ address 0x00000000 (Data = 0xEA000006)
Downloading 4 bytes @ address 0x20000000 - Verified OK
Read 4 bytes @ address 0x00000000 (Data = 0xEA000006)
Downloading 4 bytes @ address 0xFFFFEA00 - Verified OK
Read 4 bytes @ address 0x00000000 (Data = 0xEA000006)
Downloading 4 bytes @ address 0x20000000 - Verified OK
Read 4 bytes @ address 0x00000000 (Data = 0xEA000006)
Downloading 4 bytes @ address 0xFFFFEA00 - Verified OK
Read 4 bytes @ address 0x00000000 (Data = 0xEA000006)
Downloading 4 bytes @ address 0x20000000 - Verified OK
Read 4 bytes @ address 0x00000000 (Data = 0xEA000006)
Downloading 4 bytes @ address 0xFFFFEA00 - Verified OK
Read 4 bytes @ address 0x00000000 (Data = 0xEA000006)
Downloading 4 bytes @ address 0x20000000 - Verified OK
Read 4 bytes @ address 0x00000000 (Data = 0xEA000006)
Downloading 4 bytes @ address 0xFFFFEA00 - Verified OK
Read 4 bytes @ address 0x00000000 (Data = 0xEA000006)
Downloading 4 bytes @ address 0x20000000 - Verified OK
Read 4 bytes @ address 0x00000000 (Data = 0xEA000006)
Downloading 4 bytes @ address 0xFFFFEA00 - Verified OK
Read 4 bytes @ address 0x00000000 (Data = 0xEA000006)
Downloading 4 bytes @ address 0x20000000 - Verified OK
Read 4 bytes @ address 0x00000000 (Data = 0xEA000006)
Downloading 4 bytes @ address 0xFFFFEA00 - Verified OK
Read 4 bytes @ address 0x00000000 (Data = 0xEA000006)
Downloading 4 bytes @ address 0x20000000 - Verified OK
Read 4 bytes @ address 0x00000000 (Data = 0xEA000006)
Downloading 4 bytes @ address 0xFFFFEA00 - Verified OK
Read 4 bytes @ address 0x00000000 (Data = 0xEA000006)
Downloading 4 bytes @ address 0x20000000 - Verify failed
Read 4 bytes @ address 0x00000000 (Data = 0xEA000006)
Downloading 4 bytes @ address 0xFFFFEA04 - Verified OK
Read 4 bytes @ address 0x00000000 (Data = 0xEA000006)
Downloading 4080 bytes @ address 0x20000000 - Verified OK
********************************
2) In my program I allocate a memory of 5 MB and try to reset the
values to zero. During my reset the value 0 is written to multiple
locations which are 4MB apart. Why is that happening? Is this
something to do with init_sdram.gdb file configurations?
A sample of the problem:
uint nMemSize = 1024*1024*5;
uchar* pMemory = (uchar*)malloc(nMemSize);
uchar* pPtr = pMemory;
int ii = 0;
for( ii = 0 ; ii < nMemSize ; ii++)
{
*pPtr = 0 ;
pPtr++;
}
In the sample code when *pPtr =0 is executed the value 0 is written
to the address pPtr is pointing to and also to other addresses which
are 4MB apart(i.e pPtr + 4Mb, pPtr+8Mb..).
Writing to SDRAM location in AT91SAM9RL64-EK problem
Started by ●February 20, 2009
Reply by ●February 21, 20092009-02-21
--- In A..., "sananan82" wrote:
> 2) In my program I allocate a memory of 5 MB and try to reset the
> values to zero. During my reset the value 0 is written to multiple
> locations which are 4MB apart. Why is that happening? Is this
> something to do with init_sdram.gdb file configurations?
>
Most likely, it's not that the value is WRITTEN to multiple locations.
Much more likely is that your addressing is wrong, and you're READING
back the same 4 MB over and over again in your address space.
> 2) In my program I allocate a memory of 5 MB and try to reset the
> values to zero. During my reset the value 0 is written to multiple
> locations which are 4MB apart. Why is that happening? Is this
> something to do with init_sdram.gdb file configurations?
>
Most likely, it's not that the value is WRITTEN to multiple locations.
Much more likely is that your addressing is wrong, and you're READING
back the same 4 MB over and over again in your address space.
Reply by ●February 23, 20092009-02-23
--- In A..., "twgbonehead"
wrote:
>
> --- In A..., "sananan82" wrote:
>
> > 2) In my program I allocate a memory of 5 MB and try to reset the
> > values to zero. During my reset the value 0 is written to multiple
> > locations which are 4MB apart. Why is that happening? Is this
> > something to do with init_sdram.gdb file configurations?
> > Most likely, it's not that the value is WRITTEN to multiple locations.
> Much more likely is that your addressing is wrong, and you're READING
> back the same 4 MB over and over again in your address space.
>
My for loop is stopped after like half of the iterations. This is
because my stack is erased and nMemSize = 0. I am not sure why my stack
is erased which is like at the end of SDRAM (65MB) and my program is at
the beginning of SDRAM.
wrote:
>
> --- In A..., "sananan82" wrote:
>
> > 2) In my program I allocate a memory of 5 MB and try to reset the
> > values to zero. During my reset the value 0 is written to multiple
> > locations which are 4MB apart. Why is that happening? Is this
> > something to do with init_sdram.gdb file configurations?
> > Most likely, it's not that the value is WRITTEN to multiple locations.
> Much more likely is that your addressing is wrong, and you're READING
> back the same 4 MB over and over again in your address space.
>
My for loop is stopped after like half of the iterations. This is
because my stack is erased and nMemSize = 0. I am not sure why my stack
is erased which is like at the end of SDRAM (65MB) and my program is at
the beginning of SDRAM.
Reply by ●February 24, 20092009-02-24
It makes sense looking at your problem (coupling of memories which are 4 MB
apart)..
Are you doing anything with MMU? It might be that the address locations 4-8-12..MB are virtually based on address 0, and therefore when you write there, they are written as well?
Regards,
Bekir
________________________________
Von: A... [mailto:A...] Im Auftrag von sananan82
Gesendet: Montag, 23. Februar 2009 19:16
An: A...
Betreff: [AT91SAM] Re: Writing to SDRAM location in AT91SAM9RL64-EK problem
--- In A..., "twgbonehead"
wrote:
>
> --- In A..., "sananan82" wrote:
>
> > 2) In my program I allocate a memory of 5 MB and try to reset the
> > values to zero. During my reset the value 0 is written to multiple
> > locations which are 4MB apart. Why is that happening? Is this
> > something to do with init_sdram.gdb file configurations?
> > Most likely, it's not that the value is WRITTEN to multiple locations.
> Much more likely is that your addressing is wrong, and you're READING
> back the same 4 MB over and over again in your address space.
>
My for loop is stopped after like half of the iterations. This is
because my stack is erased and nMemSize = 0. I am not sure why my stack
is erased which is like at the end of SDRAM (65MB) and my program is at
the beginning of SDRAM.
Are you doing anything with MMU? It might be that the address locations 4-8-12..MB are virtually based on address 0, and therefore when you write there, they are written as well?
Regards,
Bekir
________________________________
Von: A... [mailto:A...] Im Auftrag von sananan82
Gesendet: Montag, 23. Februar 2009 19:16
An: A...
Betreff: [AT91SAM] Re: Writing to SDRAM location in AT91SAM9RL64-EK problem
--- In A..., "twgbonehead"
wrote:
>
> --- In A..., "sananan82" wrote:
>
> > 2) In my program I allocate a memory of 5 MB and try to reset the
> > values to zero. During my reset the value 0 is written to multiple
> > locations which are 4MB apart. Why is that happening? Is this
> > something to do with init_sdram.gdb file configurations?
> > Most likely, it's not that the value is WRITTEN to multiple locations.
> Much more likely is that your addressing is wrong, and you're READING
> back the same 4 MB over and over again in your address space.
>
My for loop is stopped after like half of the iterations. This is
because my stack is erased and nMemSize = 0. I am not sure why my stack
is erased which is like at the end of SDRAM (65MB) and my program is at
the beginning of SDRAM.
Reply by ●February 24, 20092009-02-24
Only I am using the init_sdram.gdb file to initialize the sdram which
is posted in the first message. Other than that I didn't use
anything. I modified the board_cstarup.S(in at91lib) file to call the
constructors and destructors for C++ program. Here is the text of
that file
/* -------------------------------
---------
* ATMEL Microcontroller Software Support - ROUSSET -
* -------------------------------
---------
* Copyright (c) 2006, Atmel Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
are met:
*
* - Redistributions of source code must retain the above copyright
notice,
* this list of conditions and the disclaimer below.
*
* - Redistributions in binary form must reproduce the above
copyright notice,
* this list of conditions and the disclaimer below in the
documentation and/or
* other materials provided with the distribution.
*
* Atmel`s name may not be used to endorse or promote products
derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY
EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-
INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//--------------------------------
----------
// Headers
//--------------------------------
----------
#include "board.h"
//--------------------------------
----------
// Definitions
//--------------------------------
----------
#define IRQ_STACK_SIZE 8*3*4
#define ARM_MODE_ABT 0x17
#define ARM_MODE_FIQ 0x11
#define ARM_MODE_IRQ 0x12
#define ARM_MODE_SVC 0x13
#define I_BIT 0x80
#define F_BIT 0x40
//--------------------------------
----------
// Startup routine
//--------------------------------
----------
.align 4
.arm
/* Exception vectors
*******************/
.section .vectors, "a", %progbits
resetVector:
ldr pc, =resetHandler /* Reset */
undefVector:
b undefVector /* Undefined instruction */
swiVector:
b swiVector /* Software interrupt */
prefetchAbortVector:
b prefetchAbortVector /* Prefetch abort */
dataAbortVector:
b dataAbortVector /* Data abort */
reservedVector:
b reservedVector /* Reserved for future use */
irqVector:
b irqHandler /* Interrupt */
fiqVector:
/* Fast interrupt */
//--------------------------------
----------
/// Handles a fast interrupt request by branching to the address
defined in the
/// AIC.
//--------------------------------
----------
fiqHandler:
b fiqHandler
//--------------------------------
----------
/// Handles incoming interrupt requests by branching to the
corresponding
/// handler, as defined in the AIC. Supports interrupt nesting.
//--------------------------------
----------
irqHandler:
/* Save interrupt context on the stack to allow nesting */
sub lr, lr, #4
stmfd sp!, {lr}
mrs lr, SPSR
stmfd sp!, {r0, lr}
/* Write in the IVR to support Protect Mode */
ldr lr, =AT91C_BASE_AIC
ldr r0, [lr, #AIC_IVR]
str lr, [lr, #AIC_IVR]
/* Branch to interrupt handler in Supervisor mode */
msr CPSR_c, #ARM_MODE_SVC
stmfd sp!, {r1-r3, r12, lr}
mov lr, pc
bx r0
/* Restore scratch/used registers and LR from User Stack */
/* Disable Interrupt and switch back in IRQ mode */
ldmia sp!, {r1-r3, r12, lr}
msr CPSR_c, #ARM_MODE_IRQ | I_BIT
/* Acknowledge interrupt */
ldr lr, =AT91C_BASE_AIC
str lr, [lr, #AIC_EOICR]
/* Restore interrupt context and branch back to calling code */
ldmia sp!, {r0, lr}
msr SPSR_cxsf, lr
ldmia sp!, {pc}^
//--------------------------------
----------
/// Initializes the chip and branches to the main() function.
//--------------------------------
----------
.section .text
.global entry
entry:
resetHandler:
/* Useless instruction for referencing the .vectors section */
ldr r0, =resetVector
/* Set pc to actual code location (i.e. not in remap zone) */
ldr pc,
/* Initialize the prerelocate segment */
1:
ldr r0, =_efixed
ldr r1, =_sprerelocate
ldr r2, =_eprerelocate
1:
cmp r1, r2
ldrcc r3, [r0], #4
strcc r3, [r1], #4
bcc 1b
/* Perform low-level initialization of the chip using LowLevelInit()
*/
ldr sp, =_sstack
stmfd sp!, {r0}
ldr r0, =LowLevelInit
mov lr, pc
bx r0
/* Initialize the postrelocate segment */
ldmfd sp!, {r0}
ldr r1, =_spostrelocate
ldr r2, =_epostrelocate
1:
cmp r1, r2
ldrcc r3, [r0], #4
strcc r3, [r1], #4
bcc 1b
/* Clear the zero segment */
ldr r0, =_szero
ldr r1, =_ezero
mov r2, #0
1:
cmp r0, r1
strcc r2, [r0], #4
bcc 1b
/* Setup stacks
**************/
/* IRQ mode */
msr CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT
ldr sp, =_sstack
sub r4, sp, #IRQ_STACK_SIZE
/* Supervisor mode (interrupts enabled) */
msr CPSR_c, #ARM_MODE_SVC | F_BIT
mov sp, r4
/* call C++ constructors of global objects */
LDR r0, =__ctors_start__
LDR r1, =__ctors_end__
ctor_loop:
CMP r0, r1
BEQ ctor_end
LDR r2, [r0], #4
STMFD sp!, {r0-r1}
MOV lr, pc
/* MOV pc, r2 */
BX r2 /* mthomas 8/2006 */
LDMFD sp!, {r0-r1}
B ctor_loop
ctor_end:
/* Branch to main()
******************/
ldr r0, =main
mov lr, pc
bx r0
/* Loop indefinitely when program is finished */
1:
b 1b
is posted in the first message. Other than that I didn't use
anything. I modified the board_cstarup.S(in at91lib) file to call the
constructors and destructors for C++ program. Here is the text of
that file
/* -------------------------------
---------
* ATMEL Microcontroller Software Support - ROUSSET -
* -------------------------------
---------
* Copyright (c) 2006, Atmel Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
are met:
*
* - Redistributions of source code must retain the above copyright
notice,
* this list of conditions and the disclaimer below.
*
* - Redistributions in binary form must reproduce the above
copyright notice,
* this list of conditions and the disclaimer below in the
documentation and/or
* other materials provided with the distribution.
*
* Atmel`s name may not be used to endorse or promote products
derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY
EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-
INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//--------------------------------
----------
// Headers
//--------------------------------
----------
#include "board.h"
//--------------------------------
----------
// Definitions
//--------------------------------
----------
#define IRQ_STACK_SIZE 8*3*4
#define ARM_MODE_ABT 0x17
#define ARM_MODE_FIQ 0x11
#define ARM_MODE_IRQ 0x12
#define ARM_MODE_SVC 0x13
#define I_BIT 0x80
#define F_BIT 0x40
//--------------------------------
----------
// Startup routine
//--------------------------------
----------
.align 4
.arm
/* Exception vectors
*******************/
.section .vectors, "a", %progbits
resetVector:
ldr pc, =resetHandler /* Reset */
undefVector:
b undefVector /* Undefined instruction */
swiVector:
b swiVector /* Software interrupt */
prefetchAbortVector:
b prefetchAbortVector /* Prefetch abort */
dataAbortVector:
b dataAbortVector /* Data abort */
reservedVector:
b reservedVector /* Reserved for future use */
irqVector:
b irqHandler /* Interrupt */
fiqVector:
/* Fast interrupt */
//--------------------------------
----------
/// Handles a fast interrupt request by branching to the address
defined in the
/// AIC.
//--------------------------------
----------
fiqHandler:
b fiqHandler
//--------------------------------
----------
/// Handles incoming interrupt requests by branching to the
corresponding
/// handler, as defined in the AIC. Supports interrupt nesting.
//--------------------------------
----------
irqHandler:
/* Save interrupt context on the stack to allow nesting */
sub lr, lr, #4
stmfd sp!, {lr}
mrs lr, SPSR
stmfd sp!, {r0, lr}
/* Write in the IVR to support Protect Mode */
ldr lr, =AT91C_BASE_AIC
ldr r0, [lr, #AIC_IVR]
str lr, [lr, #AIC_IVR]
/* Branch to interrupt handler in Supervisor mode */
msr CPSR_c, #ARM_MODE_SVC
stmfd sp!, {r1-r3, r12, lr}
mov lr, pc
bx r0
/* Restore scratch/used registers and LR from User Stack */
/* Disable Interrupt and switch back in IRQ mode */
ldmia sp!, {r1-r3, r12, lr}
msr CPSR_c, #ARM_MODE_IRQ | I_BIT
/* Acknowledge interrupt */
ldr lr, =AT91C_BASE_AIC
str lr, [lr, #AIC_EOICR]
/* Restore interrupt context and branch back to calling code */
ldmia sp!, {r0, lr}
msr SPSR_cxsf, lr
ldmia sp!, {pc}^
//--------------------------------
----------
/// Initializes the chip and branches to the main() function.
//--------------------------------
----------
.section .text
.global entry
entry:
resetHandler:
/* Useless instruction for referencing the .vectors section */
ldr r0, =resetVector
/* Set pc to actual code location (i.e. not in remap zone) */
ldr pc,
/* Initialize the prerelocate segment */
1:
ldr r0, =_efixed
ldr r1, =_sprerelocate
ldr r2, =_eprerelocate
1:
cmp r1, r2
ldrcc r3, [r0], #4
strcc r3, [r1], #4
bcc 1b
/* Perform low-level initialization of the chip using LowLevelInit()
*/
ldr sp, =_sstack
stmfd sp!, {r0}
ldr r0, =LowLevelInit
mov lr, pc
bx r0
/* Initialize the postrelocate segment */
ldmfd sp!, {r0}
ldr r1, =_spostrelocate
ldr r2, =_epostrelocate
1:
cmp r1, r2
ldrcc r3, [r0], #4
strcc r3, [r1], #4
bcc 1b
/* Clear the zero segment */
ldr r0, =_szero
ldr r1, =_ezero
mov r2, #0
1:
cmp r0, r1
strcc r2, [r0], #4
bcc 1b
/* Setup stacks
**************/
/* IRQ mode */
msr CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT
ldr sp, =_sstack
sub r4, sp, #IRQ_STACK_SIZE
/* Supervisor mode (interrupts enabled) */
msr CPSR_c, #ARM_MODE_SVC | F_BIT
mov sp, r4
/* call C++ constructors of global objects */
LDR r0, =__ctors_start__
LDR r1, =__ctors_end__
ctor_loop:
CMP r0, r1
BEQ ctor_end
LDR r2, [r0], #4
STMFD sp!, {r0-r1}
MOV lr, pc
/* MOV pc, r2 */
BX r2 /* mthomas 8/2006 */
LDMFD sp!, {r0-r1}
B ctor_loop
ctor_end:
/* Branch to main()
******************/
ldr r0, =main
mov lr, pc
bx r0
/* Loop indefinitely when program is finished */
1:
b 1b
